Harika Manem

According to our database, Harika Manem authored at least 15 papers between 2008 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Design Considerations for Memristive Crossbar Physical Unclonable Functions.

Mesbah Uddin, Md. Badruddoja Majumder, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady, Garrett S. Rose

ACM J. Emerg. Technol. Comput. Syst., 2018

2017

Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices.

Karsten Beckmann, Harika Manem, Nathaniel C. Cady

IEEE Trans. Emerg. Top. Comput., 2017

2016

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits.

Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors.

Harika Manem, Karsten Beckmann, Min Xu, Robert Carroll, Robert E. Geer, Nathaniel C. Cady

Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

2012

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.

Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Energy-Efficient Memristive Threshold Logic Circuit.

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose

IEEE Trans. Computers, 2012

Leveraging Memristive Systems in the Construction of Digital Logic Circuits.

Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino

Proc. IEEE, 2012

Design Considerations for Multilevel CMOS/Nano Memristive Memory.

Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose

ACM J. Emerg. Technol. Comput. Syst., 2012

2011

An Approach to Tolerate Process Related Variations in Memristor-Based Applications.

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A read-monitored write circuit for 1T1M multi-level memristor memories.

Harika Manem, Garrett S. Rose

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Memristor based programmable threshold logic array.

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.

Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Inversion schemes for sublithographic programmable logic arrays.

Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon

IET Comput. Digit. Tech., 2009

The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.

Harika Manem, Garrett S. Rose

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.

Harika Manem, Peter C. Paliwoda, Garrett S. Rose

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008