Mehrdad Majzoobi

According to our database1, Mehrdad Majzoobi authored at least 19 papers between 2008 and 2016.

Collaborative distances:



In proceedings 
PhD thesis 




A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators.
IEEE Trans. Multi-Scale Computing Systems, 2016

Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching.
IEEE Trans. Emerging Topics Comput., 2014

Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines.
IACR Cryptology ePrint Archive, 2014

BIST-PUF: online, hardware-based evaluation of physically unclonable circuit identifiers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Efficient Power and Timing Side Channels for Physical Unclonable Functions.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

Low-power resource binding by postsilicon customization.
ACM Trans. Design Autom. Electr. Syst., 2013

Combined Modeling and Side Channel Attacks on Strong PUFs.
IACR Cryptology ePrint Archive, 2013

Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching.
Proceedings of the 2012 IEEE Symposium on Security and Privacy Workshops, 2012

Time-Bounded Authentication of FPGAs.
IEEE Trans. Information Forensics and Security, 2011

Ultra-low power current-based PUF.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Hybrid modeling of non-stationary process variations.
Proceedings of the 48th Design Automation Conference, 2011

FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

Nonparametric combinatorial regression for shape constrained modeling.
IEEE Trans. Signal Processing, 2010

FPGA PUF using programmable delay lines.
Proceedings of the 2010 IEEE International Workshop on Information Forensics and Security, 2010

Rapid FPGA delay characterization using clock synthesis and sparse sampling.
Proceedings of the 2011 IEEE International Test Conference, 2010

FPGA Time-Bounded Unclonable Authentication.
Proceedings of the Information Hiding - 12th International Conference, 2010

Techniques for Design and Implementation of Secure Reconfigurable PUFs.
TRETS, 2009

Testing Techniques for Hardware Security.
Proceedings of the 2008 IEEE International Test Conference, 2008

Lightweight secure PUFs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008