Mehrdad Reshadi

According to our database1, Mehrdad Reshadi authored at least 25 papers between 2002 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2015
A case for application-managed cache for browser.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015

A flexible platform for QoE-driven delivery of image-rich web applications.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015

2014
MuscalietJS: rethinking layered dynamic web runtimes.
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2014

2013
ZOOMM: a parallel web browser engine for multicore mobile devices.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Improved type specialization for dynamic scripting languages.
Proceedings of the DLS'13, 2013

2012
Multidimensional dynamic behavior in mobile computing.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

2009
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.
ACM Trans. Embed. Comput. Syst., 2009

2008
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs.
ACM Trans. Reconfigurable Technol. Syst., 2008

C-based design flow: a case study on G.729A for voice over internet protocol (VoIP).
Proceedings of the 45th Design Automation Conference, 2008

2007
Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A retargetable framework for instruction-set architecture simulation.
ACM Trans. Embed. Comput. Syst., 2006

Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths .
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Graph Based Algorithm for Data Path Optimization in Custom Processors.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Generic netlist representation for system and PE level design exploration.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Designing a custom architecture for DCT using NISC technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation.
Proceedings of the 2005 Design, 2005

Memory access optimizations in instruction-set simulators.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A cycle-accurate compilation algorithm for custom pipelined datapaths.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Fast and efficient voltage scheduling by evolutionary slack distribution.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Reducing Compilation Time Overhead in Compiled Simulators.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.
Proceedings of the 40th Design Automation Conference, 2003

An efficient retargetable framework for instruction-set simulation.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002


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