Michael G. Dimopoulos
Orcid: 0000-0002-5475-2887Affiliations:
- IMAG, Grenoble, France
According to our database1,
Michael G. Dimopoulos
authored at least 26 papers
between 2002 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
IEEE Trans. Sustain. Comput., 2021
2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2014
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip.
Microprocess. Microsystems, 2014
2013
Closed-form expressions for the coupling capacitance of metal fill tiles in VLSI circuits.
Microelectron. J., 2013
Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI.
Microelectron. J., 2013
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2011
Wavelet Analysis for the Detection of Parametric and Catastrophic Faults in Mixed-Signal Circuits.
IEEE Trans. Instrum. Meas., 2011
A Nondestructive Method for Accurately Extracting Substrate Parameters of Arbitrary Doping Profile in Nanoscale VLSI.
IEEE Trans. Instrum. Meas., 2011
An evolutionary method for efficient computation of mutual capacitance for VLSI circuits based on the method of images.
Simul. Model. Pract. Theory, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Efficient inductance calculation for long and medium length rectangular interconnects in VLSI circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
IEEE Trans. Instrum. Meas., 2010
Testing Parametric and Catastrophic Faults in Mixed-Signal Integrated Circuits Using Wavelets.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
A GA-based method for efficient interconnect capacitance computation in mixed-signal integrated circuits using sets of linear charges.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Design and development of a versatile testing system for analog and mixed-signal circuits.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2004
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques.
Proceedings of the 2004 Design, 2004
2003
Accelerating the compaction of test sequences in sequential circuits through problem size reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
2002
Using Non-uniform Crossover in Genetic Algorithm Methods to Speed up the Generation of Test Patterns for Sequential Circuits.
Proceedings of the Methods and Applications of Artificial Intelligence, 2002