Nacer-Eddine Zergainoh

According to our database1, Nacer-Eddine Zergainoh authored at least 62 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2020
A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips.
IEEE Trans. Emerg. Top. Comput., 2020

2019
NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip.
Proceedings of the IEEE Latin American Test Symposium, 2019

2018
Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., 2018

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
IEEE Trans. Computers, 2018

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

A soft-error resilient route computation unit for 3D Networks-on-Chips.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips.
VLSI Design, 2017

Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations.
J. Comput. Networks Commun., 2017

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Low cost rollback to improve fault-tolerance in VLSI circuits.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Addressing transient routing errors in fault-tolerant Networks-on-Chips.
Proceedings of the 21th IEEE European Test Symposium, 2016

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
Evaluating SEU fault-injection on parallel applications implemented on multicore processors.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2014
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip.
Microprocess. Microsystems, 2014

Preliminary results of SEU fault-injection on multicore processors in AMP mode.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study.
J. Electron. Test., 2013

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Variability-aware and fault-tolerant self-adaptive applications for many-core chips.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.
J. Low Power Electron., 2011

Self-Recovering Parallel Applications in Multi-core Systems.
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

Variability-aware task mapping strategies for many-cores processor chips.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Towards a tool for implementing delay-free ECC in embedded memories.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.
Proceedings of the 16th European Test Symposium, 2011

Eliminating speed penalty in ECC protected memories.
Proceedings of the Design, Automation and Test in Europe, 2011

A fault-tolerant deadlock-free adaptive routing for on chip interconnects.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems.
Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010

2009
Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2007
Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip.
Des. Autom. Embed. Syst., 2007

Buffer Size Reduction through Control-Flow Decomposition.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems.
EURASIP J. Adv. Signal Process., 2006

2005
Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation.
Tech. Sci. Informatiques, 2005

Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip.
Int. J. Embed. Syst., 2005

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Scheduler implementation in MP SoC design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip.
Ann. des Télécommunications, 2004

2003
An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Proceedings of the 2003 Design, 2003

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Proceedings of the Embedded Software for SoC, 2003

2002
Exploration de l'espace des solutions architecturales dans le codesign.
Tech. Sci. Informatiques, 2002

Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.
IEEE Trans. Software Eng., 2002

2001
An efficient architecture model for systematic design of application-specific multiprocessor SoC.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Interlanguage Communication Synthesis for Heterogeneous Specifications.
Des. Autom. Embed. Syst., 2000

Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

Generic Architecture Platform for Multiprocessor System-On-Chip Design.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Towards design and validation of mixed-technology SOCs.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Communication Interface Synthesis for Multilanguage Specifications.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Multilanguage design of heterogeneous systems.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1994
A Real Time Multiprocessor Application Development Environment Design And Implementation.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994


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