Patrice Quinton

According to our database1, Patrice Quinton
  • authored at least 66 papers between 1976 and 2015.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2015
Combining execution pipelines to improve parallel implementation of HMMER on FPGA.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

2014
Disruption-Tolerant Wireless Sensor Networking for Biomedical Monitoring in Outdoor Conditions - Monitoring the Cardiac Activity of Marathon Runners using DTN Techniques.
MONET, 2014

2013
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

2012
Circuits parallèles à l'Irisa dans les années 1980.
Technique et Science Informatiques, 2012

Cardiac Monitoring of Marathon Runners Using Disruption-Tolerant Wireless Sensors.
Proceedings of the Ubiquitous Computing and Ambient Intelligence, 2012

Efficient hardware implementation of data-flow parallel embedded systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Biomedical Monitoring of Non-hospitalized Subjects Using Disruption-Tolerant Wireless Sensors.
Proceedings of the Wireless Mobile Communication and Healthcare, 2012

Disruption-tolerant wireless sensor networking for biomedical monitoring in outdoor conditions.
Proceedings of the 7th International Conference on Body Area Networks, 2012

Intellectual Property (IP) Integration Approach for Data-Flow Parallel Embedded Systems.
Proceedings of the e-Infrastructure and e-Services for Developing Countries, 2012

2011
Scheduling Algorithms.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Disruption-tolerant wireless biomedical monitoring for marathon runners: A feasibility study.
Proceedings of the 14th International Symposium on Wireless Personal Multimedia Communications, 2011

ompVerify: Polyhedral Analysis for the OpenMP Programmer.
Proceedings of the OpenMP in the Petascale Era - 7th International Workshop on OpenMP, 2011

Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010
Hardware Acceleration of HMMER on FPGAs.
Signal Processing Systems, 2010

Accelerating HMMER on FPGA using parallel prefixes and reductions.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems.
J. Parallel Distrib. Comput., 2009

2008
Hardware synthesis for systems of recurrence equations with multidimensional schedule.
IJES, 2008

2007
Parallelizing HMMER for Hardware Acceleration on FPGAs.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Acceleration of a content-based image-retrieval application on the RDISK cluster.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2004
Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform.
Proceedings of the Computer Systems: Architectures, 2004

Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Hardware Synthesis for Multi-Dimensional Time.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Scheduling reductions on realistic machines.
SPAA, 2002

Structured Scheduling of Recurrence Equations: Theory and Practice.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

2001
Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

2000
Derivation of systolic algorithms for the algebraic path problem by recurrence transformations.
Parallel Computing, 2000

Automatic Design of VLSI Pipelined LMS Architectures.
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

1998
Linear Programming Models for Scheduling Systems of Affine Recurrence Equations - A Comparative Study.
SPAA, 1998

1997
On Manipulating Z-Polyhedra Using a Canonical Representation.
Parallel Processing Letters, 1997

1996
Design and Implementation of a Parallel Architecture for Biological Sequence Comparison.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
A Shift Registered-Based Systolic Array for the Unbounded Knapsack Problem.
Parallel Processing Letters, 1995

On deriving data parallel code from a functional program.
Proceedings of IPPS '95, 1995

Deriving Imperative Code from Functional Programs.
Proceedings of the seventh international conference on Functional programming languages and computer architecture, 1995

1994
From Equations to Hardware. Towards the Systematic Mapping of Algorithms onto Parallel Architectures.
IJPRAI, 1994

Systolic Arrays: Why and How?
Proceedings of the Parcella 1994, 1994

Pure Systolic Array for a Class of Dynamic Dependency Recurrences.
Proceedings of the Parcella 1994, 1994

Towards a multi-formalism framework for architectural synthesis: the ASAR project.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Verification of regular architectures using ALPHA: a case study.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
Computability of recurrence equations.
Theor. Comput. Sci., 1993

Introduction to the special issue on algorithms and architectures.
Integration, 1993

1992
Systolic Convolution of Arithmetic Functions.
Theor. Comput. Sci., 1992

From Equations to Hardware: Towards Systematic Mapping of Algorithms onto Parallel Architectures.
Proceedings of the Parallel Image Analysis, Second International Conference, 1992

Efficient Linear Systolic Array for the Knapsack Problem.
Proceedings of the Parallel Processing: CONPAR 92, 1992

1991
The ALPHA language and its use for the design of systolic arrays.
VLSI Signal Processing, 1991

The Palindrome Systolic Array Revisited.
Proceedings of the Research Directions in High-Level Parallel Programming Languages, 1991

Algorithms and Parallel VLSI Architectures.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

The Alpha du Centaur environment.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

Systolic algorithms and architectures.
Prentice Hall, ISBN: 978-0-13-880790-0, 1991

1990
Synthesis of a New Systolic Architecture for the Algebraic Path Problem.
Sci. Comput. Program., 1990

1989
The mapping of linear recurrence equations on regular arrays.
VLSI Signal Processing, 1989

Systolic Gaussian Elimination over GF(p) with Partial Pivoting.
IEEE Trans. Computers, 1989

Alpha du centaur: a prototype environment for the design of parallel regular alorithms.
Proceedings of the 3rd international conference on Supercomputing, 1989

1987
Systolic solution of linear systems over GF(p) with partial pivoting.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1986
Systolic architectures for connected speech recognition.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1986

An Introduction to Systolic Architectures.
Proceedings of the Future Parallel Computers, 1986

1984
Automatic Synthesis of Systolic Arrays from Uniform Recurrent Equations.
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

A VLSI parallel machine for speech recognition.
Proceedings of the IEEE International Conference on Acoustics, 1984

1983
A Theorem-Prover for a Decidable Subset of Default Logic.
Proceedings of the National Conference on Artificial Intelligence. Washington, 1983

1982
A Network for the Detection of Words in Continuous Speech.
Acta Inf., 1982

Constructing parallel programs and their termination proof.
Proceedings of the International Conference on Parallel Processing, 1982

From speech recognition to speech understanding : A case study of Keal.
Proceedings of the IEEE International Conference on Acoustics, 1982

A systolic algorithm for connected word recognition.
Proceedings of the IEEE International Conference on Acoustics, 1982

1976
A syntactic analyzer adapted to speech recognition.
Proceedings of the IEEE International Conference on Acoustics, 1976

A multi-purpose speech recognition system.
Proceedings of the IEEE International Conference on Acoustics, 1976


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