Miguel A. Aguirre

Orcid: 0000-0002-9233-3528

According to our database1, Miguel A. Aguirre authored at least 18 papers between 1997 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

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Bibliography

2017
Contrast of a HDL model and COTS version of a microprocessor for soft-error testing.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2014
On the modelling of SEU effects on spread spectrum wireless systems.
Proceedings of the 2014 IEEE International Conference on Wireless for Space and Extreme Environments, 2014

Two complementary approaches for studying the effects of SEUs on HDL-based designs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Early assessment of SEU sensitivity through untestable fault identification.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Exploiting Fault Model Correlations to Accelerate SEU Sensitivity Assessment.
IEEE Trans. Ind. Informatics, 2013

Selective Harmonic Mitigation Technique for Cascaded H-Bridge Converters With Nonequal DC Link Voltages.
IEEE Trans. Ind. Electron., 2013

Implementation of a machine vision system for real-time traffic sign recognition on FPGA.
Proceedings of the IECON 2013, 2013

2012
Compiler-Directed Soft Error Mitigation for Embedded Systems.
IEEE Trans. Dependable Secur. Comput., 2012

2011
Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs.
IEEE Trans. Ind. Electron., 2011

Soft core based embedded systems in critical aerospace applications.
J. Syst. Archit., 2011

2010
A compiler-based infrastructure for fault-tolerant co-design.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Noninvasive Fault Classification, Robustness and Recovery Time Measurement in Microprocessor-Type Architectures Subjected to Radiation-Induced Errors.
IEEE Trans. Instrum. Meas., 2009

2008
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A Flexible Selective Harmonic Mitigation Technique to Meet Grid Codes in Three-Level PWM Converters.
IEEE Trans. Ind. Electron., 2007

2005
Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems.
Microprocess. Microsystems, 2005

1999
Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
A new field programmable system-on-a-chip for mixed signal integration.
Proceedings of the European Design and Test Conference, 1997


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