Michelangelo Grosso

Orcid: 0000-0002-9726-0356

According to our database1, Michelangelo Grosso authored at least 62 papers between 2005 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test.
Proceedings of the IEEE European Test Symposium, 2024

AMBEATion: Analog Mixed-Signal Back-End Design Automation with Machine Learning and Artificial Intelligence Techniques.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Targeting different defect-oriented fault models in IC testing: an experimental approach.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Recent Trends and Perspectives on Defect-Oriented Testing.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

A comparative overview of ATPG flows targeting traditional and cell-aware fault models.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Comparing different solutions for testing resistive defects in low-power SRAMs.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

2020
On the test of single via related defects in digital VLSI designs.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
An Investigation on Pervasive Technologies for IoT-based Thermal Monitoring.
Sensors, 2019

Software-Based Self-Test for Delay Faults.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Software-Based Self-Test for Transition Faults: a Case Study.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2018
An energy-autonomous wireless sensor network development platform.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017
Training a classifier for activity recognition using body motion simulation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Distributed Software Infrastructure for Evaluating the Integration of Photovoltaic Systems in Urban Districts.
Proceedings of the SMARTGREENS 2016, 2016

Energy-efficient battery charging in electric vehicles with solar panels.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

A compact IGBT electro-thermal model in Verilog-A for fast system-level simulation.
Proceedings of the IECON 2016, 2016

A blocking probability study for the aethereal network-on-chip.
Proceedings of the 11th International Design & Test Symposium, 2016

2015
Addressing the Smart Systems design challenge: The SMAC platform.
Microprocess. Microsystems, 2015

A new distributed framework for integration of district energy data from heterogeneous devices.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Multi-domain simulation as a foundation for the engineering of smart systems: Challenges and the SMAC vision.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Exploiting Fault Model Correlations to Accelerate SEU Sensitivity Assessment.
IEEE Trans. Ind. Informatics, 2013

On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors.
Proceedings of the 8th International Design and Test Symposium, 2013

2012
On the use of embedded debug features for permanent and transient fault resilience in microprocessors.
Microprocess. Microsystems, 2012

Software-Based Testing for System Peripherals.
J. Electron. Test., 2012

On-line software-based self-test of the Address Calculation Unit in RISC processors.
Proceedings of the 17th IEEE European Test Symposium, 2012

A SBST strategy to test microprocessors' Branch Target Buffer.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Functional Verification of DMA Controllers.
J. Electron. Test., 2011

A Low-Cost Emulation System for Fast Co-verification and Debug.
Proceedings of the 16th European Test Symposium, 2011

An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Fault grading of software-based self-test procedures for dependable automotive applications.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs.
IEEE Trans. Dependable Secur. Comput., 2010

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug.
IET Comput. Digit. Tech., 2010

A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Functional test generation for DMA controllers.
Proceedings of the 11th Latin American Test Workshop, 2010

A programmable BIST for DRAM testing and diagnosis.
Proceedings of the 2011 IEEE International Test Conference, 2010

A novel scalable and reconfigurable emulation platform for embedded systems verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

An on-line fault detection technique based on embedded debug features.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A software-based self-test methodology for system peripherals.
Proceedings of the 15th European Test Symposium, 2010

An adaptive tester architecture for volume diagnosis.
Proceedings of the 15th European Test Symposium, 2010

2009
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Evaluating Alpha-induced soft errors in embedded microprocessors.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Automatic Functional Stress Pattern Generation for SoC Reliability Characterization.
Proceedings of the 14th IEEE European Test Symposium, 2009

2008
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.
Proceedings of the Applications of Evolutionary Computing, 2008

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs.
Proceedings of the 13th European Test Symposium, 2008

2007
A System-layer Infrastructure for SoC Diagnosis.
J. Electron. Test., 2007

Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.
Proceedings of the 12th European Test Symposium, 2007

An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Safety Evaluation of NanoFabrics.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
System-in-Package Testing: Problems and Solutions.
IEEE Des. Test Comput., 2006

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

On the Automation of the Test Flow of Complex SoCs.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Embedded Memory Diagnosis: An Industrial Workflow.
Proceedings of the 2006 IEEE International Test Conference, 2006

Test Considerations about the Structured ASIC Paradigm.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Integrating BIST Techniques for On-Line SoC Testing.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs.
Proceedings of the 10th European Test Symposium, 2005


  Loading...