Luca Cassano

Pegdwende Romaric Nikiema

Antonio Miele

CoRR, 2023

Towards Dependable RISC-V Cores for Edge Computing Devices.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses.

[BibT_eX]

[DOI]

Alessandro Palumbo

Marco Ottavi

Jorge Eduardo Ortiz Trivino

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures.

[BibT_eX]

[DOI]

ACM Trans. Internet Things, 2022

Approximation-Based Fault Tolerance in Image Processing Applications.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Fault Impact Estimation for Lightweight Fault Detection in Image Filtering.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer.

[BibT_eX]

[DOI]

Alessandro Palumbo

Bruno Luzzi

José Alberto Hernández

Pedro Reviriego

Giuseppe Bianchi

Marco Ottavi

J. Syst. Archit., 2022

DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

Is RISC-V ready for Space? A Security Perspective.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

Selective Hardening of CNNs based on Layer Vulnerability Estimation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021

On the Optimization of Behavioral Logic Locking for High-Level Synthesis.

[BibT_eX]

[DOI]

CoRR, 2021

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

A Neural Network Based Fault Management Scheme for Reliable Image Processing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

A methodology for the design and deployment of distributed cyber-physical systems for smart environments.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2020

Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Microprocessor Protection Architecture against Hardware Trojans in Memories.

[BibT_eX]

[DOI]

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Lightweight Fault Detection and Management for Image Restoration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

An Approximation-based Fault Detection Scheme for Image Processing Applications.

[BibT_eX]

[DOI]

Matteo Biasielli

Antonio Miele

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

A Smart Fault Detection Scheme for Reliable Image Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

OLT(RE)<sup>2</sup>: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

2017

A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

2016

A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

UA<sup>2</sup>TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Integr., 2016

Adapting the Duty Cycle to Traffic Load in a Preamble Sampling MAC for WSNs: Formal Specification and Performance Evaluation.

[BibT_eX]

[DOI]

Ad Hoc Sens. Wirel. Networks, 2016

Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis.

[BibT_eX]

[DOI]

Antonio Miele

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2015

A configurable board-level adaptive incremental diagnosis technique based on decision trees.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2014

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Early assessment of SEU sensitivity through untestable fault identification.

[BibT_eX]

[DOI]

Hipólito Guzmán-Miranda

Miguel A. Aguirre

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel adaptive fault tolerant flip-flop architecture based on TMR.

[BibT_eX]

[DOI]

Alberto Bosio

Giorgio Di Natale

Proceedings of the 19th IEEE European Test Symposium, 2014

An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Machine learning-based techniques for incremental functional diagnosis: A comparative analysis.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014

2013

Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs.

[BibT_eX]

[DOI]

PhD thesis, 2013

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs.

[BibT_eX]

[DOI]

Mario G. C. A. Cimino

J. Syst. Archit., 2013

Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries.

[BibT_eX]

[DOI]

Proceedings of the IECON 2013, 2013

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

On-line testing of permanent radiation effects in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Formal approaches to SEU testing in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012

SEU-X: A SEu un-excitability prover for SRAM-FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Failure Probability and Fault Observability of SRAM-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Failure probability of SRAM-FPGA systems with Stochastic Activity Networks.

[BibT_eX]

[DOI]