Mikaël Briday

According to our database, Mikaël Briday authored at least 22 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems.

Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou

Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023

Design and verification of pipelined circuits with Timed Petri Nets.

Rémi Parrot, Mikaël Briday, Olivier H. Roux

Discret. Event Dyn. Syst., March, 2023

Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems.

Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux

Discret. Event Dyn. Syst., March, 2023

Securing a RISC-V architecture: A dynamic approach.

Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, A. Sintzoff, J. R. Coulon

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021

Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds.

Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange

Proceedings of the AM '21: Audio Mostly 2021, 2021

Pipeline Optimization using a Cost Extension of Timed Petri Nets.

Rémi Parrot, Mikaël Briday, Olivier H. Roux

Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design.

Rémi Parrot, Mikaël Briday, Olivier H. Roux

Proceedings of the Application and Theory of Petri Nets and Concurrency, 2021

2018

Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection.

Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement

Proceedings of the 14th European Dependable Computing Conference, 2018

HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems.

Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017

WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction.

Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou

Proceedings of the Verification and Evaluation of Computer and Communication Systems, 2017

2016

BEST: a Binary Executable Slicing Tool.

Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou

Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

Hardware runtime verification of embedded software in SoPC.

Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement

Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

2014

Improving processor hardware compiled cycle accurate simulation using program abstraction.

Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet

Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques, 2014

Reactive embedded device driver synthesis using logical timed models.

Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux

Proceedings of the 4th International Conference On Simulation And Modeling Methodologies, 2014

2013

Device driver synthesis for embedded systems.

Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux

Proceedings of 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation, 2013

2012

Harmless, a hardware architecture description language dedicated to real-time embedded system simulation.

Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet

J. Syst. Archit., 2012

2011

An Architecture Description Language for Embedded Hardware Platforms.

Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem

Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2011

Extending Harmless architecture description language for embedded real-time systems validation.

Jean-Luc Béchennec, Mikaël Briday, Valere Alibert

Proceedings of the Industrial Embedded Systems (SIES), 2011

2010

ViPER: a lightweight approach to the simulation of distributed and embedded software.

Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif

Proceedings of the 3rd International Conference on Simulation Tools and Techniques, 2010

2009

Instruction set simulator generation using HARMLESS, a new hardware architecture description language.

Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton

Proceedings of the 2nd International Conference on Simulation Tools and Techniques for Communications, 2009

2008

Simulator generation using an automaton based pipeline model for timing analysis.

Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton

Proceedings of the International Multiconference on Computer Science and Information Technology, 2008

2006

Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification.

Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet

Proceedings of 11th IEEE International Conference on Emerging Technologies and Factory Automation, 2006