Jean-Roch Coulon

According to our database, Jean-Roch Coulon authored at least 5 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture.

Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart, Nils Wistoff, Zexin Fu, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Jean-Baptiste Rigaud, Olivier Potin, Jean-Roch Coulon, César Fuguet, Luca Benini, Davide Rossi

CoRR, May, 2025

Eliminating Write-After-Write Hazards to Improve Performance in Embedded Processors.

Côme Allart, Junheng Zheng, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud

Proceedings of the 28th Euromicro Conference on Digital System Design, 2025

2024

Using a Performance Model to Implement a Superscalar CVA6.

Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023

Securing a RISC-V architecture: A dynamic approach.

Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Implementation and Performance Evaluation of Bit Manipulation Extension on CVA6 RISC-V.

Muhammad Ijaz, Fatima Saleem, Umer Shahid, Saad Waheed, Jean-Roch Coulon

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023