Min-Shueh Yuan

According to our database1, Min-Shueh Yuan authored at least 6 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply.
J. Solid-State Circuits, 2018

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013


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