Chao-Chieh Li
Orcid: 0000-0003-1159-699X
According to our database1,
Chao-Chieh Li
authored at least 9 papers
between 2015 and 2021.
Collaborative distances:
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Bibliography
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
IEEE Trans. Circuits Syst., 2020
IEEE J. Solid State Circuits, 2020
2019
A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply.
IEEE J. Solid State Circuits, 2018
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015