Hsien-Yuan Liao

According to our database1, Hsien-Yuan Liao authored at least 5 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2009
Harmonic Control Network for 2.6 GHz CMOS Class-F Power Amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Design formula for band-switching capacitor array in wide tuning range low-phase-noise LC-VCO.
Microelectron. J., 2008


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