Masanori Hariyama
Orcid: 0000-0002-1464-8807
According to our database1,
Masanori Hariyama
authored at least 96 papers
between 1994 and 2022.
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Bibliography
2022
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU.
J. Supercomput., 2022
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators.
J. Supercomput., 2022
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services.
IEEE Trans. Cloud Comput., 2022
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory.
IEEE Access, 2022
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
2020
J. Real Time Image Process., 2020
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism.
IEEE Access, 2020
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020
2019
J. Supercomput., 2019
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability.
IEEE Access, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019
Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation.
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019
2018
Proceedings of the Supercomputing Frontiers - 4th Asian Conference, 2018
A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints.
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL.
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
Proceedings of the Principles and Structures of FPGAs., 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions.
Int. J. Reconfigurable Comput., 2017
Int. J. Networked Distributed Comput., 2017
Proceedings of the 18th IEEE/ACIS International Conference on Software Engineering, 2017
2016
Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform.
IEEE Trans. Parallel Distributed Syst., 2016
J. Adv. Comput. Intell. Intell. Informatics, 2016
Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016
Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Hardware-oriented succinct-data-structure based on block-size-constrained compression.
Proceedings of the 7th International Conference of Soft Computing and Pattern Recognition, 2015
2014
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation.
J. Comput. Eng., 2014
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures.
J. Multiple Valued Log. Soft Comput., 2013
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Inf. Syst., 2013
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
IEICE Trans. Electron., 2012
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst., 2012
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation.
IEICE Trans. Electron., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors.
IEEE Trans. Circuits Syst. Video Technol., 2011
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals?
J. Multiple Valued Log. Soft Comput., 2011
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.
IEICE Trans. Electron., 2011
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals.
IEICE Trans. Inf. Syst., 2010
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture.
IEICE Trans. Electron., 2009
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment.
IEICE Trans. Electron., 2008
IEICE Trans. Inf. Syst., 2008
IEICE Trans. Electron., 2008
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture.
IEICE Trans. Electron., 2008
FPGA implementation of a vehicle detection algorithm using three-dimensional information.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
2006
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages.
IEEE Trans. Computers, 2005
J. Robotics Mechatronics, 2005
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access.
IEICE Trans. Inf. Syst., 2005
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2004
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
2002
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
2001
Proceedings of the 2001 IEEE International Conference on Robotics and Automation, 2001
2000
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction.
J. Robotics Mechatronics, 2000
J. Robotics Mechatronics, 2000
J. Robotics Mechatronics, 2000
1998
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products.
Proceedings of the IEEE International Conference on Robotics and Automation, 1998
1997
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects.
Syst. Comput. Jpn., 1997
1996
Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects.
J. Robotics Mechatronics, 1996
1994
Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles.
J. Robotics Mechatronics, 1994