Hideyuki Ozaki

According to our database, Hideyuki Ozaki authored at least 14 papers between 1986 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.

Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

2003

A Low Power Embedded DRAM Macro for Battery-Operated LSIs.

Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2001

Design methodology of embedded DRAM with virtual-socket architecture.

Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2001

2000

High-performance embedded SOI DRAM architecture for the low-power supply.

Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs.

Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki

IEEE J. Solid State Circuits, 2000

1998

400-MHz random column operating SDRAM techniques with self-skew compensation.

Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

1996

A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory.

Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.

Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.

Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

1995

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's.

Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki

IEEE J. Solid State Circuits, April, 1995

1994

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs.

Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki

IEEE J. Solid State Circuits, April, 1994

An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM.

Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, M. Suwa, Hideyuki Ozaki

IEEE J. Solid State Circuits, March, 1994

1986

Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.

Y. Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1986, 1986