Masaru Haraguchi

According to our database1, Masaru Haraguchi authored at least 8 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2011
A Scalable Massively Parallel Processor for Real-Time Image Processing.
IEEE J. Solid State Circuits, 2011

2010
A scalable massively parallel processor for real-time image processing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test.
IEICE Trans. Electron., 2009

2007
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.
IEICE Trans. Electron., 2005

2003
A Low Power Embedded DRAM Macro for Battery-Operated LSIs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2000
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.
IEEE J. Solid State Circuits, 2000


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