According to our database1, Mohammad AlFailakawi authored at least 31 papers between 2000 and 2020.
Legend:Book In proceedings Article PhD thesis Other
Optimizing scheduling decisions of container management tool using many-objective genetic algorithm.
Concurrency and Computation: Practice and Experience, 2020
FPGA-based implementation of cuckoo search.
IET Computers & Digital Techniques, 2019
Hardware accelerator for solving 0-1 knapsack problems using binary harmony search.
Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Odd/Even Invert coding for phase change memory with thermal crosstalk.
Microprocess. Microsystems, 2017
Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits.
IET Computers & Digital Techniques, 2017
Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Implementation of harmony search on embedded platform.
Microprocess. Microsystems, 2016
Harmony-search algorithm for 2D nearest neighbor quantum circuits realization.
Expert Syst. Appl., 2016
Non-volatile look-up table based FPGA implementations.
Proceedings of the 11th International Design & Test Symposium, 2016
Depth optimization for topological quantum circuits.
Quantum Information Processing, 2015
Line ordering of reversible circuits for linear nearest neighbor realization.
Quantum Information Processing, 2013
Broadcast scheduling in packet radio networks using Harmony Search algorithm.
Expert Syst. Appl., 2012
Fault model and test procedure for phase change memory.
IET Computers & Digital Techniques, 2011
Switched positive/negative charge pump design using standard CMOS transistors.
IET Circuits, Devices & Systems, 2010
Frequency assignment problem in satellite communications using differential evolution.
Comput. Oper. Res., 2010
Low-power test in compression-based reconfigurable scan architectures.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Cost-free low-power test in compression-based reconfigurable scan designs.
Proceedings of the 5th International Design and Test Workshop, 2010
Test power reduction in compression-based reconfigurable scan architectures.
Proceedings of the 15th European Test Symposium, 2010
Analysis and test procedures for NOR flash memory defects.
Microelectron. Reliab., 2008
Testing Flash Memories for Tunnel Oxide Defects.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Techniques for Disturb Fault Collapsing.
J. Electronic Testing, 2007
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Switched Polarity Charge Pump for NOR-type Flash Memories.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Optimizing program disturb fault tests using defect-based testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005
Fault collapsing for flash memory disturb faults.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005
Electrical Model For Program Disturb Faults in Non-Volatile Memories.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Stress Test for Disturb Faults in Non-Volatile Memories.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Fault Models and Test Procedures for Flash Memory Disturbances.
J. Electronic Testing, 2001
Flash Memory Disturbances: Modeling and Test.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Testing Flash Memories.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000