Mohammad AlFailakawi

Orcid: 0000-0002-7426-5402

Affiliations:
  • Kuwait University
  • University of Wisconsin Madison, WI, USA (PhD 2002)


According to our database1, Mohammad AlFailakawi authored at least 38 papers between 2000 and 2023.

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Bibliography

2023
A Spark-Based Parallel Implementation of Arithmetic Optimization Algorithm.
Int. J. Appl. Metaheuristic Comput., 2023

2022
FP-SMA: an adaptive, fluctuant population strategy for slime mould algorithm.
Neural Comput. Appl., 2022

Container scheduling techniques: A Survey and assessment.
J. King Saud Univ. Comput. Inf. Sci., 2022

2021
Parallel and Distributed Implementation of Sine Cosine Algorithm on Apache Spark Platform.
IEEE Access, 2021

Adaptation of Population Size in Sine Cosine Algorithm.
IEEE Access, 2021

2020
Machine learning-based auto-scaling for containerized applications.
Neural Comput. Appl., 2020

Optimizing scheduling decisions of container management tool using many-objective genetic algorithm.
Concurr. Comput. Pract. Exp., 2020

Apache Spark Implementation of Whale Optimization Algorithm.
Clust. Comput., 2020

2019
FPGA-based implementation of cuckoo search.
IET Comput. Digit. Tech., 2019

2018
Hardware accelerator for solving 0-1 knapsack problems using binary harmony search.
Int. J. Parallel Emergent Distributed Syst., 2018

Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
Odd/Even Invert coding for phase change memory with thermal crosstalk.
Microprocess. Microsystems, 2017

Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits.
IET Comput. Digit. Tech., 2017

Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Implementation of harmony search on embedded platform.
Microprocess. Microsystems, 2016

Harmony-search algorithm for 2D nearest neighbor quantum circuits realization.
Expert Syst. Appl., 2016

Non-volatile look-up table based FPGA implementations.
Proceedings of the 11th International Design & Test Symposium, 2016

2015
Depth optimization for topological quantum circuits.
Quantum Inf. Process., 2015

2013
Line ordering of reversible circuits for linear nearest neighbor realization.
Quantum Inf. Process., 2013

2012
Broadcast scheduling in packet radio networks using Harmony Search algorithm.
Expert Syst. Appl., 2012

2011
Fault model and test procedure for phase change memory.
IET Comput. Digit. Tech., 2011

2010
Switched positive/negative charge pump design using standard CMOS transistors.
IET Circuits Devices Syst., 2010

Frequency assignment problem in satellite communications using differential evolution.
Comput. Oper. Res., 2010

Low-power test in compression-based reconfigurable scan architectures.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Cost-free low-power test in compression-based reconfigurable scan designs.
Proceedings of the 5th International Design and Test Workshop, 2010

Test power reduction in compression-based reconfigurable scan architectures.
Proceedings of the 15th European Test Symposium, 2010

2008
Analysis and test procedures for NOR flash memory defects.
Microelectron. Reliab., 2008

Testing Flash Memories for Tunnel Oxide Defects.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
Techniques for Disturb Fault Collapsing.
J. Electron. Test., 2007

2006
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Switched Polarity Charge Pump for NOR-type Flash Memories.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Optimizing program disturb fault tests using defect-based testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Fault collapsing for flash memory disturb faults.
Proceedings of the 10th European Test Symposium, 2005

2003
Electrical Model For Program Disturb Faults in Non-Volatile Memories.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Stress Test for Disturb Faults in Non-Volatile Memories.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2001
Fault Models and Test Procedures for Flash Memory Disturbances.
J. Electron. Test., 2001

Flash Memory Disturbances: Modeling and Test.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000
Testing Flash Memories.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000


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