Mohammad Hossein Moaiyeri

Orcid: 0000-0001-9711-7923

According to our database1, Mohammad Hossein Moaiyeri authored at least 66 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
On the Layout-Oriented Investigation of Power Attack Hardness of Spintronic-Based Logic Circuits.
Circuits Syst. Signal Process., May, 2024

Low-Cost and Variation-Aware Spintronic Ternary Random Number Generator.
Circuits Syst. Signal Process., February, 2024

2023
Ultra-efficient fully programmable membership function generator based on independent double-gate FinFET technology.
Int. J. Circuit Theory Appl., October, 2023

A look-up table-based processing-in-SRAM architecture for energy-efficient search applications.
Comput. Electr. Eng., September, 2023

A high-capacity and nonvolatile spintronic associative memory hardware accelerator.
IET Circuits Devices Syst., July, 2023

A Fast and Light Fingerprint-Matching Model Based on Deep Learning Approaches.
J. Signal Process. Syst., April, 2023

An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient Applications.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Hardware-accuracy trade-offs for error-resilient applications using an ultra-efficient hybrid approximate multiplier.
J. Supercomput., 2023

High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator.
IEEE Trans. Emerg. Top. Comput., 2023

A Flexible and Reliable RRAM-Based In-Memory Computing Architecture for Data-Intensive Applications.
IEEE Trans. Emerg. Top. Comput., 2023

A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier.
IEEE Access, 2023

2022
Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons.
IEEE Trans. Emerg. Top. Comput., 2022

Energy- and Quality-Efficient Approximate Multipliers for Neural Network and Image Processing Applications.
IEEE Trans. Emerg. Top. Comput., 2022

Correction to "Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware".
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A process variation resilient spintronic true random number generator for highly reliable hardware security applications.
Microelectron. J., 2022

A Hardware- and Accuracy-Efficient Approximate Multiplier with Error Compensation for Neural Network and Image Processing Applications.
Circuits Syst. Signal Process., 2022

A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology.
IEEE Access, 2022

2021
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic.
Microelectron. J., 2021

Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors.
Int. J. Circuit Theory Appl., 2021

Ultra-Compact Imprecise 4: 2 Compressor and Multiplier Circuits for Approximate Computing in Deep Nanoscale.
Circuits Syst. Signal Process., 2021

Ultra-High-Performance Magnetic Nonvolatile Level Converter Flip-Flop with Spin-Hall Assistance for Dual-Supply Systems with Power Gating Architecture.
Circuits Syst. Signal Process., 2021

Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology.
IEEE Access, 2021

MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Stochastic Spintronic Neuron with Application to Image Binarization.
Proceedings of the 26th International Computer Conference, Computer Society of Iran, 2021

2020
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.
Microelectron. J., 2020

NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design.
Circuits Syst. Signal Process., 2020

A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors.
Comput. Electr. Eng., 2020

Low-Cost Implementation of Bilinear and Bicubic Image Interpolation for Real-Time Image Super-Resolution.
Proceedings of the IEEE Global Humanitarian Technology Conference, 2020

2019
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs.
IEEE Trans. Fuzzy Syst., 2018

An energy and area efficient 4: 2 compressor based on FinFETs.
Integr., 2018

An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic.
Circuits Syst. Signal Process., 2018

2017
Quantum-dot cellular automata circuits with reduced external fixed inputs.
Microprocess. Microsystems, 2017

High Performance CNFET-based Ternary Full Adders.
CoRR, 2017

2016
CNFET-based approximate ternary adders for energy-efficient image processing applications.
Microprocess. Microsystems, 2016

Design and analysis of carbon nanotube FET based quaternary full adders.
Frontiers Inf. Technol. Electron. Eng., 2016

An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs.
J. Low Power Electron., 2016

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques.
Circuits Syst. Signal Process., 2016

A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology.
CoRR, 2016

2015
Designing efficient QCA logical circuits with power dissipation analysis.
Microelectron. J., 2015

Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach.
Microelectron. J., 2015

Designing quantum-dot cellular automata counters with energy consumption analysis.
Microprocess. Microsystems, 2015

A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter.
J. Circuits Syst. Comput., 2015

High-performance ternary logic gates for nanoelectronics.
Int. J. High Perform. Syst. Archit., 2015

2013
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits.
IET Comput. Digit. Tech., 2013

An efficient cntfet-based 7-input minority gate
CoRR, 2013

Dramatically Low-Transistor-Count High-Speed Ternary Adders.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

2012
An Energy-Efficient Full Adder Cell Using CNFET Technology.
IEICE Trans. Electron., 2012

A new SPICE model for organic molecular transistors and a novel hybrid architecture.
IEICE Electron. Express, 2012

Design and Evaluation of CNFET-Based Quaternary Circuits.
Circuits Syst. Signal Process., 2012

High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology.
Circuits Syst. Signal Process., 2012

A New Full Adder Cell for Molecular Electronics
CoRR, 2012

2011
Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata.
Microelectron. J., 2011

A New Robust and High-Performance Hybrid Full Adder Cell.
J. Circuits Syst. Comput., 2011

High-speed full adder based on minority function and bridge style for nanoscale.
Integr., 2011

Design of energy-efficient and robust ternary circuits for nanotechnology.
IET Circuits Devices Syst., 2011

A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders.
Fuzzy Sets Syst., 2011

Design and Evaluating Carbon Nanotube Interconnects for a Generic Delta MIN.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

Comparative Performance Study of Multi-stage Interconnection Networks Using Carbon Nanotube Switches.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

2009
Two new low-power Full Adders based on majority-not gates.
Microelectron. J., 2009

Two New Low-Power and High-Performance Full Adders.
J. Comput., 2009

2008
Ultra high speed Full Adders.
IEICE Electron. Express, 2008


  Loading...