Somayeh Timarchi

According to our database1, Somayeh Timarchi authored at least 21 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix.
Microelectron. J., 2019

Optimized Parity-Based Error Detection and Correction Methods for Residue Number System.
J. Circuits Syst. Comput., 2019

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2<sup><i>n</i></sup> - 1 Adder and Multiplier.
Circuits Syst. Signal Process., 2019

2018
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Low-power DCT-based compressor for wireless capsule endoscopy.
Signal Process. Image Commun., 2017

2016
Efficient modulo 2<sup>n</sup> +1 multiplier.
Int. J. Comput. Aided Eng. Technol., 2016

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques.
Circuits Syst. Signal Process., 2016

Ultra-low voltage standard cell libraries: Design strategies and a case study.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Fast architecture for decimal digit multiplication.
Microprocess. Microsystems, 2015

2014
High-speed energy-efficient 5: 2 compressor.
Proceedings of the 37th International Convention on Information and Communication Technology, 2014

2013
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}.
IET Comput. Digit. Tech., 2012

2010
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2<sup>n</sup> -1, 2<sup>n</sup>, 2<sup>n</sup> +1, 2<sup>2n + 1</sup>-1 and 2<sup>n</sup> -1, 2<sup>n</sup> +1, 2<sup>2n</sup>, 2<sup>2n</sup> +1 Based on New CRTs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A unified addition structure for moduli set {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} based on a novel RNS representation.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Arithmetic Circuits of Redundant SUT-RNS.
IEEE Trans. Instrum. Meas., 2009

A novel low-power full-adder cell for low voltage.
Integr., 2009

A new algorithm for determining all possible symmetric hybrid redundant numbers.
IEICE Electron. Express, 2009

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2005
Evaluation of Some Exponential Random Number Generators Implemented by FPGA.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005


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