Somayeh Timarchi

According to our database, Somayeh Timarchi authored at least 28 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling.

Mina Raouf, Somayeh Timarchi

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors.

Ladan Sayadi, Somayeh Timarchi, Akbar Sheikh-Akbari

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

High-Performance Memory Allocation on FPGA With Reduced Internal Fragmentation.

Mohammad Mehdi Gilanian Sadeghi, Somayeh Timarchi, Mahmood Fazlali

IEEE Access, 2023

2022

Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization.

Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid

Microprocess. Microsystems, September, 2022

Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography.

Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor.

Seyed Amir Hossein Ejtahed, Somayeh Timarchi

Circuits Syst. Signal Process., 2022

2021

Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem.

Ahmad Shabani, Mohammad Sabri, Bahareh Khabbazan, Somayeh Timarchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles.

Hossein Mahdavi, Somayeh Timarchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019

Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC.

Hossein Mahdavi, Somayeh Timarchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix.

Ahmad Shabani, Somayeh Timarchi, Hossein Mahdavi

Microelectron. J., 2019

Optimized Parity-Based Error Detection and Correction Methods for Residue Number System.

Adib Armand, Somayeh Timarchi, Hossein Mahdavi

J. Circuits Syst. Comput., 2019

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2^<i>n</i> - 1 Adder and Multiplier.

Somayeh Timarchi, Negar Akbarzadeh

Circuits Syst. Signal Process., 2019

2018

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates.

Hamed Naseri, Somayeh Timarchi

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

Low-power DCT-based compressor for wireless capsule endoscopy.

Ahmad Shabani, Somayeh Timarchi

Signal Process. Image Commun., 2017

2016

Efficient modulo 2ⁿ +1 multiplier.

Masoud Abbasi Alaie, Somayeh Timarchi

Int. J. Comput. Aided Eng. Technol., 2016

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques.

Majid Moghaddam, Somayeh Timarchi, Mohammad Hossein Moaiyeri, Mohammad Eshghi

Circuits Syst. Signal Process., 2016

Ultra-low voltage standard cell libraries: Design strategies and a case study.

Somayeh Timarchi, Massimo Alioto

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Fast architecture for decimal digit multiplication.

Mahmood Fazlali, Hadi Valikhani, Somayeh Timarchi, Hadi Tabatabaee Malazi

Microprocess. Microsystems, 2015

2014

High-speed energy-efficient 5: 2 compressor.

Ardalan Najafi, Somayeh Timarchi, Amir Najafi

Proceedings of the 37th International Convention on Information and Communication Technology, 2014

2013

High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding.

Somayeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012

Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2ⁿ - 1, 2ⁿ, 2ⁿ + 1}.

Somayeh Timarchi, Mahmood Fazlali

IET Comput. Digit. Tech., 2012

2010

Efficient Reverse Converter Designs for the New 4-Moduli Sets 2ⁿ -1, 2ⁿ, 2ⁿ +1, 2^{2n + 1}-1 and 2ⁿ -1, 2ⁿ +1, 2²ⁿ, 2²ⁿ +1 Based on New CRTs.

Amir Sabbagh Molahosseini, Keivan Navi, Chitra Dadkhah, Omid Kavehei, Somayeh Timarchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A unified addition structure for moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1} based on a novel RNS representation.

Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana

Proceedings of the 28th International Conference on Computer Design, 2010

2009

Arithmetic Circuits of Redundant SUT-RNS.

Somayeh Timarchi, Keivan Navi

IEEE Trans. Instrum. Meas., 2009

A novel low-power full-adder cell for low voltage.

Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei

Integr., 2009

A new algorithm for determining all possible symmetric hybrid redundant numbers.

Somayeh Timarchi, Keivan Navi

IEICE Electron. Express, 2009

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation.

Somayeh Timarchi, Keivan Navi, Omid Kavehei

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2005

Evaluation of Some Exponential Random Number Generators Implemented by FPGA.

Somayeh Timarchi, Seyed Ghassem Miremadi, Ali Reza Ejlali

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005