Reza Faghih Mirzaee
Orcid: 0000-0001-7175-0229
According to our database1,
Reza Faghih Mirzaee
authored at least 42 papers
between 2008 and 2023.
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Bibliography
2023
Design and evaluation of ultra-fast 8-bit approximate multipliers using novel multicolumn inexact compressors.
Int. J. Circuit Theory Appl., July, 2023
Comprehensive survey of ternary full adders: Statistics, corrections, and assessments.
IET Circuits Devices Syst., May, 2023
2022
Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement.
IEEE Access, 2022
2021
Microelectron. J., 2021
J. Circuits Syst. Comput., 2021
Ultra-Fast, High-Performance 8x8 Approximate Multipliers by a New Multicolumn 3, 3: 2 Inexact Compressor and its Derivatives.
CoRR, 2021
2020
A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET.
J. Circuits Syst. Comput., 2020
Multi valued parity generator based on Sudoku tables: properties and detection probability.
IET Commun., 2020
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source.
IET Comput. Digit. Tech., 2020
2019
Int. J. High Perform. Syst. Archit., 2019
Circuits Syst. Signal Process., 2019
MIPS-Core Application Specific Instruction-Set Processor for IDEA Cryptography - Comparison between Single-Cycle and Multi-Cycle Architectures.
CoRR, 2019
2017
Nano Commun. Networks, 2017
A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs.
J. Multiple Valued Log. Soft Comput., 2017
J. Low Power Electron., 2017
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector.
J. Circuits Syst. Comput., 2017
A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates.
IET Circuits Devices Syst., 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
2016
Microelectron. J., 2016
IEICE Trans. Electron., 2016
Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic.
CoRR, 2016
Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
2015
New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources.
J. Electr. Comput. Eng., 2015
New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources.
Int. J. High Perform. Syst. Archit., 2015
Int. J. High Perform. Syst. Archit., 2015
Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic.
IET Circuits Devices Syst., 2015
2014
A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors.
J. Circuits Syst. Comput., 2014
IEICE Trans. Inf. Syst., 2014
2013
Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic.
Microelectron. J., 2013
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors.
Int. J. High Perform. Syst. Archit., 2013
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits.
IET Comput. Digit. Tech., 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
2011
J. Circuits Syst. Comput., 2011
Integr., 2011
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011
2009
2008