Amir Sabbagh Molahosseini

Orcid: 0000-0003-3603-9401

According to our database1, Amir Sabbagh Molahosseini authored at least 37 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
uLog: a software-based approximate logarithmic number system for computations on SIMD processors.
J. Supercomput., 2023

Resource-Efficient Convolutional Networks: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
ACM Comput. Surv., 2023

2022
A joint computational and resource allocation model for fast parallel data processing in fog computing.
J. Supercomput., 2022

Image processing with high-speed and low-energy approximate arithmetic circuit.
Sustain. Comput. Informatics Syst., 2022

Hunter-prey optimization: algorithm and applications.
Soft Comput., 2022

Zero-Aware Low-Precision RNS Scaling Scheme.
Axioms, 2022

Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific.
Proceedings of the Approximate Computing, 2022

2021
A fault-tolerant architecture for internet-of-things based on software-defined networks.
Telecommun. Syst., 2021

Efficient Incorporation of the RNS Datapath in Reverse Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Increasing fault tolerance of data plane on the internet of things using the software-defined networks.
PeerJ Comput. Sci., 2021

Resource-Efficient Deep Learning: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
CoRR, 2021

Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration.
Comput. Electr. Eng., 2021

A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set.
Comput. Sci., 2021

2020
Half-Precision Floating-Point Formats for PageRank: Opportunities and Challenges.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding.
IEEE Trans. Very Large Scale Integr. Syst., 2019

New energy-efficient hybrid wide-operand adder architecture.
IET Circuits Devices Syst., 2019

2018
Towards Efficient Modular Adders based on Reversible Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2<sup>k</sup>, 2<sup>P</sup>-1}.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2<sup>n</sup> + 1 Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Residue-to-binary conversion for general moduli sets based on approximate Chinese remainder theorem.
Int. J. Comput. Math., 2017

A Multifunctional Unit for Designing Efficient RNS-Based Datapaths.
IEEE Access, 2017

2016
Area-delay-power-aware adder placement method for RNS reverse converter design.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

RNS reverse converters for moduli sets with dynamic ranges of 9n-bit.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Comparison of modular numbers based on the chinese remainder theorem with fractional values.
Autom. Control. Comput. Sci., 2015

2014
Rethinking reverse converter design: From algorithms to hardware components.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2012
Efficient RNS to binary converters for the new 4-moduli set {2<sup><i>n</i></sup>, 2<sup><i>n</i>+1</sup>-1, 2<sup><i>n</i></sup>-1, 2<sup><i>n</i>-1</sup>-1}.
IEICE Electron. Express, 2012

2011
How to Teach Residue Number System to Computer Scientists and Engineers.
IEEE Trans. Educ., 2011

A General Reverse Converter Architecture with Low Complexity and High Performance.
IEICE Trans. Inf. Syst., 2011

2010
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2<sup>n</sup> -1, 2<sup>n</sup>, 2<sup>n</sup> +1, 2<sup>2n + 1</sup>-1 and 2<sup>n</sup> -1, 2<sup>n</sup> +1, 2<sup>2n</sup>, 2<sup>2n</sup> +1 Based on New CRTs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Reduced-Area Reverse Converter for the Moduli Set {2<sup>n</sup>, 2<sup>n</sup>-1, 2<sup>2n-1</sup>-1}.
Int. J. Adv. Comp. Techn., 2010

A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A new four-modulus RNS to binary converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2<sup>2<i>n</i></sup>, 2<sup><i>n</i></sup> -1, 2<sup><i>n</i>+1</sup> -1} and {2<sup>2<i>n</i></sup>, 2<sup><i>n</i></sup> -1, 2<sup><i>n</i>-1</sup> -1}.
IEICE Trans. Inf. Syst., 2009

A new five-moduli set for efficient hardware implementation of the reverse converter.
IEICE Electron. Express, 2009

2008
An efficient architecture for designing reverse converters based on a general three-moduli set.
J. Syst. Archit., 2008

An improved reverse converter for the moduli set {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1}.
IEICE Electron. Express, 2008


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