Mohammad Reza Reshadinezhad

Orcid: 0000-0003-4859-9879

According to our database1, Mohammad Reza Reshadinezhad authored at least 11 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
New design for error-resilient approximate multipliers used in image processing in CNTFET technology.
J. Supercomput., February, 2024

Energy-efficient and fast IMPLY-based approximate full adder applying NAND gates for image processing.
Comput. Electr. Eng., January, 2024

2023
Fast and Compact Serial IMPLY-Based Approximate Full Adders Applied in Image Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

2022
Approximate In-Memory Computing using Memristive IMPLY Logic and its Application to Image Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS.
Sustain. Comput. Informatics Syst., 2021

2020
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells.
IEEE Access, 2020

A Memristor-based Quaternary Memory with Adaptive Noise Tolerance.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
A new design method for imperfection-immune CNFET-based circuit design.
Microelectron. J., 2019

2018
Design of a parity preserving reversible full adder/subtractor circuit.
Int. J. Comput. Intell. Stud., 2018

2016
Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits.
Microelectron. J., 2016

2012
An Energy-Efficient Full Adder Cell Using CNFET Technology.
IEICE Trans. Electron., 2012


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