Xinli Gu

According to our database1, Xinli Gu authored at least 69 papers between 1991 and 2022.

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Bibliography

2022
Unsupervised Two-Stage Root-Cause Analysis for Integrated Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Black-Box Test-Cost Reduction Based on Bayesian Network Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Board-Level Functional Fault Identification Using Streaming Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Fine-grained Adaptive Testing Based on Quality Prediction.
ACM Trans. Design Autom. Electr. Syst., 2020

Self-Learning and Efficient Health-Status Analysis for a Core Router System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hierarchical Symbol-Based Health-Status Analysis Using Time-Series Data in a Core Router System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Unsupervised Root-Cause Analysis for Integrated Systems.
Proceedings of the IEEE International Test Conference, 2020

2019
Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Anomaly Detection and Health-Status Analysis in a Core Router System.
IEEE Des. Test, 2019

IP Session on Machine Learning Applications in IC Test-Related Tasks.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation.
Proceedings of the IEEE International Test Conference, 2019

2018
Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Self-Learning Health-Status Analysis for a Core Router System.
Proceedings of the IEEE International Test Conference, 2018

Failure prediction based on anomaly detection for complex core routers.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Symbol-based health-status analysis in a core router system.
Proceedings of the IEEE International Test Conference, 2017

Changepoint-based anomaly detection in a core router system.
Proceedings of the IEEE International Test Conference, 2017

Data-driven fault diagnosis with missing syndromes imputation for functional test through conditional specification.
Proceedings of the 22nd IEEE European Test Symposium, 2017

RetroDMR: Troubleshooting non-deterministic faults with retrospective DMR.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Accurate anomaly detection using correlation-based time-series analysis in a core router system.
Proceedings of the 2016 IEEE International Test Conference, 2016

2015
Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Self-learning and adaptive board-level functional fault diagnosis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

On test syndrome merging for reasoning-based board-level functional fault diagnosis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Information-Theoretic Framework for Evaluating and Guiding Board-Level Functional-Fault Diagnosis.
IEEE Des. Test, 2014

Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Knowledge discovery and knowledge transfer in board-level functional fault diagnosis.
Proceedings of the 2014 International Test Conference, 2014

2013
Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

AgentDiag: An agent-assisted diagnostic framework for board-level functional failures.
Proceedings of the 2013 IEEE International Test Conference, 2013

Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis.
Proceedings of the 18th IEEE European Test Symposium, 2013

Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?
Proceedings of the 18th IEEE European Test Symposium, 2013

Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Physical-Defect Modeling and Optimization for Fault-Insertion Test.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster-Shafer Theory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Reproduction and Detection of Board-Level Functional Failure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Are industrial test problems real problems? I thought research has resolved them all!
Proceedings of the 2012 IEEE International Test Conference, 2012

Diagnostic system based on support-vector machines for board-level functional diagnosis.
Proceedings of the 17th IEEE European Test Symposium, 2012

Re-using chip level DFT at board level.
Proceedings of the 17th IEEE European Test Symposium, 2012

Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

In-Field Testing of NAND Flash Storage: Why and How?
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Session Summary V: Is Component Interconnection Test Enough for Board or System Test.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Session Summary II: Dependable VLSI for Product Reliability.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks.
Proceedings of the 2011 IEEE International Test Conference, 2011

The gap: Test challenges in Asia manufacturing field.
Proceedings of the 2011 IEEE International Test Conference, 2011

Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures.
Proceedings of the 16th European Test Symposium, 2011

Deterministic test for the reproduction and detection of board-level functional failures.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Board-level fault diagnosis using Bayesian inference.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Board-level fault diagnosis using an error-flow dictionary.
Proceedings of the 2011 IEEE International Test Conference, 2010

Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Physical defect modeling for fault insertion in system reliability test.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Des. Test Comput., 2008

2006
Design for Board and System Level Structural Test and Diagnosis.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
A practical perspective on reducing ASIC NTFs.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
At-Speed Interconnect Test and Diagnosis of External Memories on a System.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Realizing High Test Quality Goals with Smart Test Resource Usage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
Re-Using DFT Logic for Functional and Silicon Debugging Test.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
An effort-minimized logic BIST implementation method.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1998
A new approach to scan chain reordering using physical design information.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
A controller testability analysis and enhancement technique.
Proceedings of the European Design and Test Conference, 1997

1995
RT level testability-driven partitioning.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

An Efficient and Economic Partitioning Approach for Testability.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Testability analysis and improvement from VHDL behavioral specifications.
Proceedings of the Proceedings EURO-DAC'94, 1994

1992
An approach to testability analysis and improvement for VLSI systems.
Microprocess. Microprogramming, 1992

1991
Testability measure with reconvergent fanout analysis and its applications.
Microprocessing and Microprogramming, 1991


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