Moritoshi Yasunaga
According to our database1,
Moritoshi Yasunaga
authored at least 70 papers
between 1990 and 2024.
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Bibliography
2024
A highly scalable Self-organizing Map accelerator on FPGA and its performance evaluation.
Artif. Life Robotics, February, 2024
A FPGA-based Learning Accelerator for Self-Organizing Map and Its Application to Trend-Visualization.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
FPGA Implementation of Minimum Spanning Tree Calculation Towards Application for Capacitated Vehicle Routing Problems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
2018
Artif. Life Robotics, 2018
2016
SIGARCH Comput. Archit. News, 2016
Artif. Life Robotics, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
2015
Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2015
Proceedings of the Parallel Computing: On the Road to Exascale, 2015
2014
Segmental transmission line: Its practical application the optimized PCB trace design using a genetic algorithm.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014
2011
Artif. Life Robotics, 2011
2010
Development of a novel crossover of hybrid genetic algorithms for large-scale traveling salesman problems.
Artif. Life Robotics, 2010
Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging.
Artif. Life Robotics, 2010
A proposal for Zoning Crossover of Hybrid Genetic Algorithms for large-scale traveling salesman problems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
2009
2008
Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera.
Artif. Life Robotics, 2008
Artif. Life Robotics, 2008
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation.
J. VLSI Signal Process., 2007
Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems.
IEEE Trans. Syst. Man Cybern. Part B, 2007
A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine.
Proceedings of the Parallel Computing: Architectures, 2007
Proceedings of the Neural Information Processing, 14th International Conference, 2007
Proceedings of the Evolvable Systems: From Biology to Hardware, 2007
Proceedings of the Applications of Evolutinary Computing, 2007
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
Enhancement of the Variable-Length-Transmission-Line design method for multi-point optimization.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
Proceedings of the IEEE Congress on Evolutionary Computation, 2005
Variable length segmental-transmission-line and its parameter optimization based on GA.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005
2004
IEICE Trans. Inf. Syst., 2004
A multimodal neural network with single-state predictions for protein secondary structure.
Artif. Life Robotics, 2004
Artif. Life Robotics, 2004
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
2003
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Reconfigurable parallel comparation architecture and its application to IP packet filters.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
The design of segmental-transmission-line for high-speed digital signals using genetic algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
2002
Proceedings of the Recent Advances in Simulated Evolution and Learning [extended and revised papers selected from the 4th Asia-Pacific Conference on Simulated Evolution and Learning, 2002
An evolutionary kernel-based reasoning system using reconfigurable VLSIs: its hardware prototyping and application to the splicing boundary problem.
Proceedings of the 2002 Congress on Evolutionary Computation, 2002
Proceedings of the 2002 Congress on Evolutionary Computation, 2002
2001
IEEE Trans. Veh. Technol., 2001
Genet. Program. Evolvable Mach., 2001
Proceedings of the 2001 Congress on Evolutionary Computation, 2001
2000
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000
A Fast Model-Building Method for Time Series Using Genetic Programming.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000
Kernel Optimization in Pattern Recognition Using a Genetic Algorithm.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables.
Proceedings of the 2nd NASA / DoD Workshop on Evolvable Hardware (EH 2000), 2000
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
GP-based modeling method for time series prediction with parameter optimization and node alternation.
Proceedings of the 2000 Congress on Evolutionary Computation, 2000
Proceedings of the 2000 Congress on Evolutionary Computation, 2000
1999
Proceedings of the International Joint Conference Neural Networks, 1999
Parallel back-propagation using genetic algorithm: real-time BP learning on the massively parallel computer CP-PACS.
Proceedings of the International Joint Conference Neural Networks, 1999
Proceedings of the International Joint Conference Neural Networks, 1999
Proceedings of the International Joint Conference Neural Networks, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains.
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998
Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions.
Proceedings of the Fifth International Conference on Neural Information Processing, 1998
1997
Ising model calculation using PDM neural network hardware: Boltzmann statistical mechanics embedded in the hardware.
Proceedings of International Conference on Neural Networks (ICNN'97), 1997
1992
Proceedings of the 10th National Conference on Artificial Intelligence, 1992
1990
Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons.
Proceedings of the IJCNN 1990, 1990