Hiroshi Nakayama

According to our database, Hiroshi Nakayama authored at least 10 papers between 1999 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs.

Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2016

Clinical big image data based pre-operative planning in ACL reconstruction.

Kento Morita, Manabu Nii, Shunichiro Kambara, Kaori Kashiwa, Hiroshi Nakayama, Shinichi Yoshiya, Syoji Kobashi

Proceedings of the International Conference on Machine Learning and Cybernetics, 2016

Blumensaat's line detection for Quadrant method on MR images.

Kento Morita, Syoji Kobashi, Kaori Kashiwa, Hiroshi Nakayama, Shunichiro Kambara, Masakazu Morimoto, Shinichi Yoshiya, Satoru Aikawa

Proceedings of the 2016 IEEE International Conference on Fuzzy Systems, 2016

2015

Computer-aided Surgical Planning of Anterior Cruciate Ligament Reconstruction in MR Images.

Kento Morita, Syoji Kobashi, Kaori Kashiwa, Hiroshi Nakayama, Shunichiro Kambara, Masakazu Morimoto, Shinichi Yoshiya, Satoru Aikawa

Proceedings of the 19th International Conference in Knowledge Based and Intelligent Information and Engineering Systems, 2015

2012

Adaptive spatial/temporal direct mode selection algorithm on H.264/AVC Encoder.

Kentaro Kawakami, Yasuhiro Watanabe, Hiroshi Nakayama

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

2010

Self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder.

Wen Ji, Makoto Hamaminato, Hiroshi Nakayama, Satoshi Goto

IEICE Electron. Express, 2010

Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging.

Masami Ishiguro, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Ikuo Yoshihara, Moritoshi Yasunaga

Artif. Life Robotics, 2010

A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder.

Wen Ji, Makoto Hamaminato, Hiroshi Nakayama, Satoshi Goto

Proceedings of the 18th European Signal Processing Conference, 2010

2008

The Segmental-Transmission-Line: Its Design and Prototype Evaluation.

Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim

Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

1999

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.

Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada

IEEE J. Solid State Circuits, 1999