Muralidaran Vijayaraghavan

According to our database, Muralidaran Vijayaraghavan authored at least 22 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Constructing a Weak Memory Model.

Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Kami: a platform for high-level parametric hardware specification and its modular verification.

Joonwon Choi, Muralidaran Vijayaraghavan, Benjamin Sherman, Adam Chlipala, Arvind

Proc. ACM Program. Lang., 2017

Weak Memory Models with Matching Axiomatic and Operational Definitions.

Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig, Arvind

CoRR, 2017

An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution.

Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind

CoRR, 2017

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility.

Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Modular verification of hardware systems.

Muralidaran Vijayaraghavan

PhD thesis, 2016

Taming Weak Memory Models.

Sizhuo Zhang, Arvind, Muralidaran Vijayaraghavan

CoRR, 2016

2015

A Proof of Correctness for the Tardis Cache Coherence Protocol.

Xiangyao Yu, Muralidaran Vijayaraghavan, Srinivas Devadas

CoRR, 2015

Modular Deductive Verification of Multiprocessor Hardware Designs.

Muralidaran Vijayaraghavan, Adam Chlipala, Arvind, Nirav Dave

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014

A new synthesis procedure for atomic rules containing multi-cycle function blocks.

Michal Karczmarek, Arvind, Muralidaran Vijayaraghavan

Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

2013

Modular compilation of guarded atomic actions.

Muralidaran Vijayaraghavan, Nirav Dave, Arvind

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2012

A general technique for deterministic model-cycle-level debugging.

Asif Khan, Muralidaran Vijayaraghavan, Arvind

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Fast and cycle-accurate modeling of a multicore processor.

Asif Khan, Muralidaran Vijayaraghavan, Silas Boyd-Wickizer, Arvind

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

2010

Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID).

Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

2009

A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs.

Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer

ACM Trans. Reconfigurable Technol. Syst., 2009

Bounded Dataflow Networks and Latency-Insensitive circuits.

Muralidaran Vijayaraghavan, Arvind

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Implementing a fast cartesian-polar matrix interpolator.

Abhinav Agarwal, Nirav Dave, Kermin Fleming, Asif Khan, Myron King, Man Cheuk Ng, Muralidaran Vijayaraghavan

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

2008

High-throughput Pipelined Mergesort.

Kermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.

Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.

Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007

From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols.

Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA.

Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007