Pranathi Vasireddy

Orcid: 0000-0003-4352-3816

According to our database1, Pranathi Vasireddy authored at least 9 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR.
ACM Trans. Reconfigurable Technol. Syst., June, 2026

Striking the Balance: GEMM Performance Optimization Across Generations of Ryzen™ AI NPUs.
Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

2025
Striking the Balance: GEMM Performance Optimization Across Generations of Ryzen AI NPUs.
CoRR, December, 2025

Can Asymmetric Tile Buffering Be Beneficial?
CoRR, November, 2025

Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface.
Proceedings of the 33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2025

2023
Streaming Sparse Data on Architectures with Vector Extensions using Near Data Processing.
Proceedings of the International Symposium on Memory Systems, 2023

2022
Memory-Side Acceleration and Sparse Compression for Quantized Packed Convolutions.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA PROCESSING.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Sparse-T: Hardware Accelerator Thread for Unstructured Sparse Data Processing.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022


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