Nanditha Rao

According to our database, Nanditha Rao authored at least 14 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs.

Himanshu Rai, Aishwarya Sridhar, Wolfgang Ecker, Nanditha Rao

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

VFMA: Scalable Floating-Point Accelerator for Vector FMA on FPGAs.

Himanshu Rai, Sasi Snigdha Yadavalli, Aishwarya Sridhar, Nanditha Rao

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

LUTAccel: Look-up-Table Based Vector Systolic Accelerator on FPGAs.

Aashish Kumar Tiwary, Saketh Gajawada, Jay Shah, Nanditha Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

FlexPE: Flexible Processing Elements for Workload Optimization and Acceleration on FPGAs.

Lasya Punya Sree Gundumogula, Rachana Kaparthi, Himanshu Rai, Nanditha Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond.

Stefan Abi-Karam, Rishov Sarkar, Allison Seigler, Sean Lowe, Zhigang Wei, Hanqiu Chen, Nanditha Rao, Lizy Kurian John, Aman Arora, Cong Hao

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Hybrid Multi-tile Vector Systolic Architecture for Accelerating Convolution on FPGAs.

Jay Shah, Nanditha Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

FPGA-based Hardware Software Co-design to Accelerate Brain Tumour Segmentation.

Vinay Rayapati, Gogireddy Ravi Kiran Reddy, Gandi Ajay Kumar, Saketh Gajawada, Sanampudi Gopala Krishna Reddy, Nanditha Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory Vector Co-Processor.

Chithambara Moorthii J, Vinay Rayapati, Nanditha Rao, Manan Suri

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

HiPC 2024 WORKSHOP 2: 1st Workshop on RecOnfigurable Computing and Systems (ROCS 2024).

Nanditha Rao, Jason Lin

Proceedings of the 31st IEEE International Conference on High Performance Computing, Data and Analytics, HiPC 2024, 2024

Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs.

Arun Iyer, Nishant Pawar, Dinesh Gaitonde, Nanditha Rao

Proceedings of the International Conference on Field Programmable Technology, 2024

2023

DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision.

Archie Mishra, Nanditha Rao

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML Benchmarks.

Anubhav Mishra, Nanditha Rao, Ganesh Gore, Xifan Tang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients.

Jhalak Sharma, Nanditha Rao

Microelectron. J., 2022

2019

Analysis of the Effect of QoS on Video Conferencing QoE.

Nanditha Rao, Amir Haghighati Maleki, Fu Chi Chen, Wenjun Chen, C. Zhang, Navneet Kaur, Anwar Haque

Proceedings of the 15th International Wireless Communications & Mobile Computing Conference, 2019