Dinesh Gaitonde

Orcid: 0000-0001-8823-9689

According to our database1, Dinesh Gaitonde authored at least 18 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

AMD Next-Generation FPGA Built from Chiplets.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021
Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
Versal Network-on-Chip (NoC).
Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

Network-on-Chip Programmable Platform in Versal<sup>TM</sup> ACAP Architecture.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Xilinx Adaptive Compute Acceleration Platform: Versal<sup>TM</sup> Architecture.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Placement Strategies for 2.5D FPGA Fabric Architectures.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A SAT-based Timing Driven Place and Route Flow for Critical Soft IP.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2016
Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
Enhancements in UltraScale CLB Architecture.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
High capacity and high performance 20nm FPGAs.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

1999
Instruction level power model of microcontrollers.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
An overview of library characterization in semi-custom design.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998


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