Naoya Niwa

According to our database, Naoya Niwa authored at least 8 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A Compression Router for Low-Latency Network-on-Chip.

Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi

IEICE Trans. Inf. Syst., February, 2023

2022

Boosting the Performance of Interconnection Networks by Selective Data Compression.

Naoya Niwa, Hideharu Amano, Michihiro Koibuchi

IEICE Trans. Inf. Syst., December, 2022

Distance Aware Compression for Low Latency High Bandwidth Interconnection Network.

Zhou Yuqing, Naoya Niwa, Hideharu Amano

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2021

A Case for Low-Latency Network-on-Chip using Compression Routers.

Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi

Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression.

Naoya Niwa, Hideharu Amano, Michihiro Koibuchi

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2019

The Case for Water-Immersion Computer Boards.

Michihiro Koibuchi, Ikki Fujiwara, Naoya Niwa, Tomohiro Totoki, Shoichi Hirasawa

Proceedings of the 48th International Conference on Parallel Processing, 2019

Sparse 3-D NoCs with Inductive Coupling.

Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization.

Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Sixth International Symposium on Computing and Networking, 2018