Naran Sirisantana

According to our database1, Naran Sirisantana authored at least 10 papers between 2000 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst., 2005

2004
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses.
IEEE Des. Test Comput., 2004

Enhancing Yield at the End of the Technology Roadmap.
IEEE Des. Test Comput., 2004

2003
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies.
Proceedings of the ESSCIRC 2003, 2003

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
Proceedings of the 2003 Design, 2003

Integer linear programming-based synthesis of skewed logic circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Skewed CMOS: noise-tolerant high-performance low-power static circuit family.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Synthesis of Selectively Clocked Skewed Logic Circuits.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000


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