Bipul Chandra Paul

  • Purdue University, West Lafayette, USA

According to our database1, Bipul Chandra Paul authored at least 36 papers between 2000 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement.
Proceedings of the IEEE International Memory Workshop, 2022

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Retrospective View on the Technology Evolution to Support Low Power Mobile Application.
J. Low Power Electron., 2018

Introduction to the special issue on memory technologies.
ACM J. Emerg. Technol. Comput. Syst., 2013

Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier.
IEEE J. Solid State Circuits, 2009

Advances in nanoelectronics circuits and systems [Editorial].
IET Comput. Digit. Tech., 2009

Optimized Circuit Failure Prediction for Aging: Practicality and Promise.
Proceedings of the 2008 IEEE International Test Conference, 2008

ROM based logic (RBL) design: High-performance and low-power adders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Prospect of ballistic CNFET in high performance applications: Modeling and analysis.
ACM J. Emerg. Technol. Comput. Syst., 2007

Circuit Failure Prediction and Its Application to Transistor Aging.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst., 2006

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low-power design techniques for scaled technologies.
Integr., 2006

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.
J. Electron. Test., 2006

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Modeling and analysis of circuit performance of ballistic CNFET.
Proceedings of the 43rd Design Automation Conference, 2006

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A process-tolerant cache architecture for improved yield in nanoscale technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Process variation in embedded memories: failure analysis and variation aware architecture.
IEEE J. Solid State Circuits, 2005

Statistical Timing Analysis using Levelized Covariance Propagation.
Proceedings of the 2005 Design, 2005

Enhancing Yield at the End of the Technology Roadmap.
IEEE Des. Test Comput., 2004

Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Device optimization for ultra-low power digital sub-threshold operation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Novel sizing algorithm for yield improvement under process variation in nanometer technology.
Proceedings of the 41th Design Automation Conference, 2004

Process variation in nano-scale memories: failure analysis and process tolerant architecture.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Adaptive supply voltage technique for low swing interconnects.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Dynamic Noise Analysis with Capacitive and Inductive Coupling.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Robust subthreshold logic for ultra-low power operation.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design Verification and Robust Design Technique for Cross-Talk Faults.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Robust ultra-low power sub-threshold DTMOS logic.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000