Bipul Chandra Paul

According to our database, Bipul Chandra Paul authored at least 36 papers between 2000 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement.

Nishtha S. Gaul, Akhilesh Jaiswal, Hongsik Yoon, Taeyoung Lee, Kazutaka Yamane, Joseph Versaggi, Rick Carter, Bipul C. Paul

Proceedings of the IEEE International Memory Workshop, 2022

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

A Retrospective View on the Technology Evolution to Support Low Power Mobile Application.

Bipul C. Paul, Ajey P. Jacob, William Taylor, Randy W. Mann, Joseph Versaggi, Edward J. Nowak, Lars W. Liebmann

J. Low Power Electron., 2018

2013

Introduction to the special issue on memory technologies.

Bipul C. Paul, Arijit Raychowdhury

ACM J. Emerg. Technol. Comput. Syst., 2013

2011

Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.

Bipul C. Paul, Arijit Raychowdhury

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2009

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier.

Bipul C. Paul, Shinobu Fujita, Masaki Okajima

IEEE J. Solid State Circuits, 2009

Advances in nanoelectronics circuits and systems [Editorial].

Bipul C. Paul, Krishnendu Chakrabarty

IET Comput. Digit. Tech., 2009

2008

Optimized Circuit Failure Prediction for Aging: Practicality and Promise.

Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra

Proceedings of the 2008 IEEE International Test Conference, 2008

ROM based logic (RBL) design: High-performance and low-power adders.

Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.

Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Prospect of ballistic CNFET in high performance applications: Modeling and analysis.

Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee

ACM J. Emerg. Technol. Comput. Syst., 2007

Circuit Failure Prediction and Its Application to Transistor Aging.

Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.

Kunhyuk Kang, Bipul C. Paul, Kaushik Roy

ACM Trans. Design Autom. Electr. Syst., 2006

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.

Aditya Bansal, Bipul Chandra Paul, Kaushik Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low-power design techniques for scaled technologies.

Bipul Chandra Paul, Amit Agarwal, Kaushik Roy

Integr., 2006

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.

Bipul C. Paul, Kaushik Roy

J. Electron. Test., 2006

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.

Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.

Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Modeling and analysis of circuit performance of ballistic CNFET.

Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee

Proceedings of the 43rd Design Automation Conference, 2006

2005

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.

Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2005

A process-tolerant cache architecture for improved yield in nanoscale technologies.

Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2005

Process variation in embedded memories: failure analysis and variation aware architecture.

Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy

IEEE J. Solid State Circuits, 2005

Statistical Timing Analysis using Levelized Covariance Propagation.

Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy

Proceedings of the 2005 Design, 2005

2004

Enhancing Yield at the End of the Technology Roadmap.

Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy

IEEE Des. Test Comput., 2004

Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.

Bipul Chandra Paul, Cassondra Neau, Kaushik Roy

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Device optimization for ultra-low power digital sub-threshold operation.

Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.

Amit Agarwal, Bipul Chandra Paul, Kaushik Roy

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Novel sizing algorithm for yield improvement under process variation in nanometer technology.

Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy

Proceedings of the 41th Design Automation Conference, 2004

Process variation in nano-scale memories: failure analysis and process tolerant architecture.

Amit Agarwal, Bipul C. Paul, Kaushik Roy

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Adaptive supply voltage technique for low swing interconnects.

Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002

Dynamic Noise Analysis with Capacitive and Inductive Coupling.

Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.

Bipul Chandra Paul, Kaushik Roy

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Robust subthreshold logic for ultra-low power operation.

Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul

IEEE Trans. Very Large Scale Integr. Syst., 2001

Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.

Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design Verification and Robust Design Technique for Cross-Talk Faults.

Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Robust ultra-low power sub-threshold DTMOS logic.

Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000