Liqiong Wei

According to our database1, Liqiong Wei authored at least 20 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 3.6Mb 10.1Mb/mm<sup>2</sup> Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015
A 0.094um<sup>2</sup> high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist.
Proceedings of the Symposium on VLSI Circuits, 2015

2011
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design.
IEEE Des. Test Comput., 2011

2010
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.
IEEE J. Solid State Circuits, 2010

2009
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits, 2008

2007
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2002
Vertically integrated SOI circuits for low-power and high-performance applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.
IEEE Des. Test Comput., 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002

2001
On effective I<sub>DDQ</sub> testing of low-voltage CMOS circuits using leakage control techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mixed-<i>V<sub>th</sub></i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
Proceedings of the 35th Conference on Design Automation, 1998


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