Dinesh Somasekhar

According to our database, Dinesh Somasekhar authored at least 38 papers between 1993 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.

Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim

IEEE Trans. Very Large Scale Integr. Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).

Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).

Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Overview of Circuits, Systems, and Applications of Spintronics.

Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2014

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits.

Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury

IEEE J. Solid State Circuits, 2014

Advanced memory topics.

Toshiaki Kirihata, Dinesh Somasekhar

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012

Direct Compare of Information Coded With Error-Correcting Codes.

Wei Wu, Dinesh Somasekhar, Shih-Lien Lu

IEEE Trans. Very Large Scale Integr. Syst., 2012

A fully-digital phase-locked low dropout regulator in 32nm CMOS.

Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De

Proceedings of the Symposium on VLSI Circuits, 2012

2011

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.

Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar

IET Comput. Digit. Tech., 2011

3DICs for tera-scale computing: a case study.

Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar

Proceedings of the 2011 International Symposium on Physical Design, 2011

2010

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.

Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang

IEEE J. Solid State Circuits, 2010

Reducing cache power with low-cost, multi-bit error-correcting codes.

Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Resilient design in scaled CMOS for energy efficiency.

James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.

Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi

IEEE J. Solid State Circuits, 2009

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.

Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De

IEEE J. Solid State Circuits, 2009

2008

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.

Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 256-Kb Dual-V_CC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

IEEE J. Solid State Circuits, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.

James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Fine-Grained Redundancy in Adders.

Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

A 4.2GHz 0.3mm2 256kb Dual-V_cc SRAM Building Block in 65nm CMOS.

Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.

Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications.

Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2003

A 6-GHz 16-kB L1 cache in a 100-nm dual-V_T technology using a bitline leakage reduction (BLR) technique.

Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De

IEEE J. Solid State Circuits, 2003

Bitline leakage equalization for sub-100nm caches.

Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson

Proceedings of the ESSCIRC 2003, 2003

2002

Skewed CMOS: noise-tolerant high-performance low-power static circuit family.

Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2002

Leakage control with efficient use of transistor stacks in single threshold CMOS.

Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2002

5-GHz 32-bit integer execution core in 130-nm dual-V_T CMOS.

Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar

IEEE J. Solid State Circuits, 2002

2000

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.

Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Dynamic noise analysis in precharge-evaluate circuits.

Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De

Proceedings of the 37th Conference on Design Automation, 2000

1999

Models and algorithms for bounds on leakage in CMOS circuits.

Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.

Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy

Proceedings of the IEEE International Conference On Computer Design, 1999

Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS.

Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy

Proceedings of the 36th Conference on Design Automation, 1999

1998

LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family.

Dinesh Somasekhar, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 1998

IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.

Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

LVDCSL: low voltage differential current switch logic, a robust low power DCSL family.

Dinesh Somasekhar, Kaushik Roy

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

Differential current switch logic: a low power DCVS logic family.

Dinesh Somasekhar, Kaushik Roy

IEEE J. Solid State Circuits, 1996

1993

A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.

Dinesh Somasekhar, V. Visvanathan

IEEE Trans. Very Large Scale Integr. Syst., 1993

A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking.

Dinesh Somasekhar, V. Visvanathan

Proceedings of the Sixth International Conference on VLSI Design, 1993