Rajesh Radhakrishnan

Orcid: 0000-0001-7170-699X

According to our database1, Rajesh Radhakrishnan authored at least 17 papers between 2000 and 2015.

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Bibliography

2015
Content discovery and retrieval services at the European Nucleotide Archive.
Nucleic Acids Res., 2015

2014
Assembly information services in the European Nucleotide Archive.
Nucleic Acids Res., 2014

EBI metagenomics - a new resource for the analysis and archiving of metagenomic data.
Nucleic Acids Res., 2014

Political engineering: optimizing a U.S. Presidential candidate's platform.
Ann. Oper. Res., 2014

2013
Facing growth in the European Nucleotide Archive.
Nucleic Acids Res., 2013

2012
Major submissions tool developments at the European nucleotide archive.
Nucleic Acids Res., 2012

2011
The European Nucleotide Archive.
Nucleic Acids Res., 2011

2010
Improvements to services at the European Nucleotide Archive.
Nucleic Acids Res., 2010

2009
Petabyte-scale innovations at the European Nucleotide Archive.
Nucleic Acids Res., 2009

Transfreight Reduces Costs and Balances Workload at Georgetown Crossdock.
Interfaces, 2009

2003
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002
Framework for Synthesis of Virtual Pipelines.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A novel MAC layer protocol for space division multiple access in wireless ad hoc networks.
Proceedings of the 11th International Conference on Computer Communications and Networks, 2002

2001
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis.
Formal Methods Syst. Des., 2001

On the verification of synthesized designs using automatically generated transformational witnesses.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Verification of Basic Block Schedules Using RTL Transformations.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
An approach to high-level synthesis system validation using formally verified transformations.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000


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