Narendra Vallepalli

According to our database1, Narendra Vallepalli authored at least 2 papers between 2005 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.
IEEE J. Solid State Circuits, 2006

2005
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.
IEEE J. Solid State Circuits, 2005


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