Zhanping Chen

According to our database1, Zhanping Chen authored at least 21 papers between 1997 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A 0.9-μm<sup>2</sup> 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming.
IEEE J. Solid State Circuits, 2017

2016
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2016

2010
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m <sup>2</sup> <i>1T1R</i> Bit Cell in 32 nm High-k Metal-Gate CMOS.
IEEE J. Solid State Circuits, 2010

2009
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.
IEEE J. Solid State Circuits, 2009

2008
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits, 2008

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2002
Vertically integrated SOI circuits for low-power and high-performance applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.
IEEE Des. Test Comput., 2002

2001
On effective I<sub>DDQ</sub> testing of low-voltage CMOS circuits using leakage control techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Estimation of power dissipation using a novel power macromodelingtechnique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1999
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mixed-<i>V<sub>th</sub></i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Estimation of power sensitivity in sequential circuits with power macromodeling application.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
Proceedings of the 35th Conference on Design Automation, 1998

A Power Macromodeling Technique Based on Power Sensitivity.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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