Nasibeh Teimouri

According to our database, Nasibeh Teimouri authored at least 8 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Alleviating Scalability Limitation of Accelerator-Based Platforms.

Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2016

Improving scalability of CMPs with dense ACCs coverage.

Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths.

Mehdi Modarressi, Nasibeh Teimouri, Hamid Sarbazi-Azad

Integr., 2015

Modeling and Analysis of SLDL-Captured NoC Abstractions.

Ran Hao, Nasibeh Teimouri, Kasra Moazzemi, Gunar Schirner

Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Revisiting accelerator-rich CMPs: challenges and solutions.

Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system.

Mohammad Khavari Tavana, Nasibeh Teimouri, Meisam Abdollahi, Maziar Goudarzi

ACM Trans. Embed. Comput. Syst., 2014

2013

Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip.

Nasibeh Teimouri, Mehdi Modarressi, Hamid Sarbazi-Azad

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

2011

Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths.

Nasibeh Teimouri, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad

Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011