Gunar Schirner
Orcid: 0000-0002-5408-8496Affiliations:
- Northeastern University, Boston, USA
According to our database1,
Gunar Schirner
authored at least 84 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on ece.neu.edu
On csauthors.net:
Bibliography
2024
CoRR, 2024
Multistatic-Radar RCS-Signature Recognition of Aerial Vehicles: A Bayesian Fusion Approach.
CoRR, 2024
2023
TSAR-ILP: Tile-Based, Synchronization-AwaRe ILP Allocating Heterogeneous Platforms for Streaming Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Generating Unified Platforms Using Multigranularity Domain DSE (MG-DmDSE) Exploiting Application Similarities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2021
CoRR, 2021
Multimodal Fusion of EMG and Vision for Human Grasp Intent Inference in Prosthetic Hand Control.
CoRR, 2021
HANDS: A Multimodal Dataset for Modeling Towards Human Grasp Intent Inference in Prosthetic Hands.
CoRR, 2021
RDP<sup>3</sup>: Rapid Domain Platform Performance Prediction for Design Space Exploration.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Classifications of Dynamic EMG in Hand Gesture and Unsupervised Grasp Motion Segmentation.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
MG-DmDSE: Multi-Granularity Domain Design Space Exploration Considering Function Similarity.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
HANDS: a multimodal dataset for modeling toward human grasp intent inference in prosthetic hands.
Intell. Serv. Robotics, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
From hand-perspective visual information to grasp type probabilities: deep learning via ranking labels.
Proceedings of the 12th ACM International Conference on PErvasive Technologies Related to Assistive Environments, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Towards Creating a Deployable Grasp Type Probability Estimator for a Prosthetic Hand.
Proceedings of the Cyber Physical Systems. Model-Based Design - 9th International Workshop, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
2016
Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications.
J. Signal Process. Syst., 2016
Multi-Path Model and Sensitivity Analysis for Galvanic Coupled Intra-Body Communication Through Layered Tissue.
IEEE Trans. Biomed. Circuits Syst., 2016
Communication and cooling aware job allocation in data centers for communication-intensive workloads.
J. Parallel Distributed Comput., 2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Framework for Rapid Development of Embedded Human-in-the-Loop Cyber-Physical Systems.
Proceedings of the 16th IEEE International Conference on Bioinformatics and Bioengineering, 2016
2015
ACM Trans. Archit. Code Optim., 2015
SIGARCH Comput. Archit. News, 2015
Conceptual Abstraction Levels (CALs) for managing design complexity of market-oriented MPSoCs.
Microprocess. Microsystems, 2015
IET Comput. Digit. Tech., 2015
Towards closing the specification gap by integrating algorithm-level and system-level design.
Des. Autom. Embed. Syst., 2015
Optimization of energy efficient relay position for galvanic coupled intra-body communication.
Proceedings of the 2015 IEEE Wireless Communications and Networking Conference, 2015
Proceedings of the Workshop on Computer Architecture Education, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015
Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Analyzing power efficiency of optimization techniques and algorithm design methods for applications on heterogeneous platforms.
Int. J. High Perform. Comput. Appl., 2014
Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs.
IEEE Embed. Syst. Lett., 2014
A GPU-Based Algorithm-Specific Optimization for High-Performance Background Subtraction.
Proceedings of the 43rd International Conference on Parallel Processing, 2014
Proceedings of the ACM/IEEE International Conference on Cyber-Physical Systems, 2014
A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the IEEE 38th Annual Computer Software and Applications Conference, 2014
Multi-path 2-Port Channel Characterization for Galvanic Coupled Intra-body Communication.
Proceedings of the 9th International Conference on Body Area Networks, 2014
Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Proceedings of the Numerical Computations with GPUs, 2014
2013
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013
Algorithm and architecture co-design of Mixture of Gaussian (MoG) background subtraction for embedded vision.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Flexible function-level acceleration of embedded vision applications using the Pipelined Vision Processor.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
AFReP: Application-guided Function-level Registerfile power-gating for embedded processors.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Application-specific power-efficient approach for reducing register file vulnerability.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE Des. Test Comput., 2011
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
2010
ACM Trans. Design Autom. Electr. Syst., 2010
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Proceedings of the Analysis, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
ACM Trans. Embed. Comput. Syst., 2008
Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling.
Proceedings of the Design, Automation and Test in Europe, 2008
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005
2004
Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems.
Proceedings of the On the Move to Meaningful Internet Systems 2004: CoopIS, 2004