Gunar Schirner

According to our database1, Gunar Schirner authored at least 68 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Alleviating Scalability Limitation of Accelerator-Based Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

From hand-perspective visual information to grasp type probabilities: deep learning via ranking labels.
Proceedings of the 12th ACM International Conference on PErvasive Technologies Related to Assistive Environments, 2019

2018
DS-DSE: Domain-specific design space exploration for streaming applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
SCE: System-on-Chip Environment.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

2016
Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications.
Signal Processing Systems, 2016

Multi-Path Model and Sensitivity Analysis for Galvanic Coupled Intra-Body Communication Through Layered Tissue.
IEEE Trans. Biomed. Circuits and Systems, 2016

Communication and cooling aware job allocation in data centers for communication-intensive workloads.
J. Parallel Distrib. Comput., 2016

Studying Inter-Warp Divergence Aware Execution on GPUs.
Computer Architecture Letters, 2016

EEGu2: an embedded device for brain/body signal acquisition and processing.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

Hardware thread reordering to boost OpenCL throughput on FPGAs.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Guiding Power/Quality Exploration for Communication-Intense Stream Processing.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Improving scalability of CMPs with dense ACCs coverage.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Framework for Rapid Development of Embedded Human-in-the-Loop Cyber-Physical Systems.
Proceedings of the 16th IEEE International Conference on Bioinformatics and Bioengineering, 2016

2015
A Joint SW/HW Approach for Reducing Register File Vulnerability.
TACO, 2015

Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA.
SIGARCH Computer Architecture News, 2015

Conceptual Abstraction Levels (CALs) for managing design complexity of market-oriented MPSoCs.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Power-efficient real-time solution for adaptive vision algorithms.
IET Computers & Digital Techniques, 2015

Towards closing the specification gap by integrating algorithm-level and system-level design.
Design Autom. for Emb. Sys., 2015

Optimization of energy efficient relay position for galvanic coupled intra-body communication.
Proceedings of the 2015 IEEE Wireless Communications and Networking Conference, 2015

Engaging sophomores in embedded design using robotics.
Proceedings of the Workshop on Computer Architecture Education, 2015

Rapid heterogeneous prototyping from Simulink.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Taming the Memory Demand Complexity of Adaptive Vision Algorithms.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Modeling and Analysis of SLDL-Captured NoC Abstractions.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Revisiting accelerator-rich CMPs: challenges and solutions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded software.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An efficient architecture solution for low-power real-time background subtraction.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Application-Guided Power Gating Reducing Register File Static Power.
IEEE Trans. VLSI Syst., 2014

Analyzing power efficiency of optimization techniques and algorithm design methods for applications on heterogeneous platforms.
IJHPCA, 2014

Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs.
Embedded Systems Letters, 2014

A GPU-Based Algorithm-Specific Optimization for High-Performance Background Subtraction.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

WiP abstract: System-level integration of mobile multi-modal multi-sensor systems.
Proceedings of the ACM/IEEE International Conference on Cyber-Physical Systems, 2014

A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Automatic specification granularity tuning for design space exploration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploring the Heterogeneous Design Space for both Performance and Reliability.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

SIROM3 - A Scalable Intelligent Roaming Multi-modal Multi-sensor Framework.
Proceedings of the IEEE 38th Annual Computer Software and Applications Conference, 2014

Multi-path 2-Port Channel Characterization for Galvanic Coupled Intra-body Communication.
Proceedings of the 9th International Conference on Body Area Networks, 2014

Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Fast Fourier Transform (FFT) on GPUs.
Proceedings of the Numerical Computations with GPUs, 2014

2013
The Future of Human-in-the-Loop Cyber-Physical Systems.
IEEE Computer, 2013

Quantifying the energy efficiency of FFT on heterogeneous platforms.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Joint Algorithm Developing and System-Level Design: Case Study on Video Encoding.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Algorithm and architecture co-design of Mixture of Gaussian (MoG) background subtraction for embedded vision.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Flexible function-level acceleration of embedded vision applications using the Pipelined Vision Processor.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

AFReP: Application-guided Function-level Registerfile power-gating for embedded processors.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Application-specific power-efficient approach for reducing register file vulnerability.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Automatic TLM Generation for Early Validation of Multicore Systems.
IEEE Design & Test of Computers, 2011

Modeling, synthesis, and validation of heterogeneous biomedical embedded systems.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2010
Fast and accurate processor models for efficient MPSoC design.
ACM Trans. Design Autom. Electr. Syst., 2010

Exploring SW performance using preemptive RTOS models.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Accurate timed RTOS model for transaction level modeling.
Proceedings of the Design, Automation and Test in Europe, 2010

System-level development of embedded software.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Platform modeling for exploration and synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support.
Proceedings of the Analysis, 2009

Hardware-dependent software synthesis for many-core embedded systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling.
ACM Trans. Embedded Comput. Syst., 2008

Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling.
Proceedings of the Design, Automation and Test in Europe, 2008

Automatic generation of hardware dependent software for MPSoCs from abstract system specifications.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Embedded Software Development in a System-Level Design Flow.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Abstract, Multifaceted Modeling of Embedded Processors for System Level Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Fast and accurate transaction level models using result oriented modeling.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Quantitative analysis of transaction level models for the AMBA bus.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Accurate yet fast modeling of real-time communication.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Abstract Communication Modeling.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

2004
Late Demarshalling: A Technique for Efficient Multi-language Middleware for Embedded Systems.
Proceedings of the On the Move to Meaningful Internet Systems 2004: CoopIS, 2004


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