Maziar Goudarzi
Orcid: 0000-0002-1272-4589
According to our database1,
Maziar Goudarzi
authored at least 81 papers
between 2003 and 2024.
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Bibliography
2024
Variant Parallelism: Lightweight Deep Convolutional Models for Distributed Inference on IoT Devices.
IEEE Internet Things J., January, 2024
2023
J. Big Data, December, 2023
J. Grid Comput., December, 2023
An Ensemble Mobile-Cloud Computing Method for Affordable and Accurate Glucometer Readout.
CoRR, 2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
2022
Infrastructure Aware Heterogeneous-Workloads Scheduling for Data Center Energy Cost Minimization.
IEEE Trans. Cloud Comput., 2022
FullPack: Full Vector Utilization for Sub-Byte Quantized Inference on General Purpose CPUs.
CoRR, 2022
2021
IEEE Trans. Cloud Comput., 2021
SVNN: an efficient PacBio-specific pipeline for structural variations calling using neural networks.
BMC Bioinform., 2021
2020
Learning-based power prediction for geo-distributed Data Centers: weather parameter analysis.
J. Big Data, 2020
Workload Scheduling on heterogeneous Mobile Edge Cloud in 5G networks to Minimize SLA Violation.
CoRR, 2020
2019
SAIR: significance-aware approach to improve QoR of big data processing in case of budget constraint.
J. Supercomput., 2019
IEEE Trans. Cloud Comput., 2019
IEEE Trans. Big Data, 2019
Evaluation of distributed stream processing frameworks for IoT applications in Smart Cities.
J. Big Data, 2019
J. Big Data, 2019
2018
J. Grid Comput., 2018
MapReduce service provisioning for frequent big data jobs on clouds considering data transfers.
Comput. Electr. Eng., 2018
Data locality and VM interference aware mitigation of data skew in hadoop leveraging modern portfolio theory.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Syst. J., 2017
Using Data Variety for Efficient Progressive Big Data Processing in Warehouse-Scale Computers.
IEEE Comput. Archit. Lett., 2017
Proceedings of the 16th International Symposium on Parallel and Distributed Computing, 2017
2016
IEEE Trans. Big Data, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Energy efficiency in cloud-based MapReduce applications through better performance estimation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Dynamically adaptive register file architecture for energy reduction in embedded processors.
Microprocess. Microsystems, 2015
Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design.
IET Comput. Digit. Tech., 2015
Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study.
IET Comput. Digit. Tech., 2015
Energy-Aware Scheduling for Precedence-Constrained Parallel Virtual Machines in Virtualized Data Centers.
J. Grid Comput., 2015
TABEMS: Tariff-Aware Building Energy Management System for Sustainability through Better Use of Electricity.
Comput. J., 2015
Structure-aware online virtual machine consolidation for datacenter energy improvement in cloud computing.
Comput. Electr. Eng., 2015
2014
Power reduction in HPC data centers: a joint server placement and chassis consolidation approach.
J. Supercomput., 2014
Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system.
ACM Trans. Embed. Comput. Syst., 2014
2013
Static statistical MPSoC power optimization by variation-aware task and communication scheduling.
Microprocess. Microsystems, 2013
Microprocess. Microsystems, 2013
2012
IET Comput. Digit. Tech., 2012
Variation-aware Server Placement and Task Assignment for Data Center Power Minimization.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies.
Trans. High Perform. Embed. Archit. Compil., 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
2010
SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2008
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V<sub>th</sub> variation.
Microelectron. J., 2008
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model.
Microprocess. Microsystems, 2008
J. Circuits Syst. Comput., 2008
IEICE Trans. Electron., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Electron. Express, 2008
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems.
J. Comput. Syst. Sci., 2007
Comput. Electr. Eng., 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs.
J. Univers. Comput. Sci., 2004
Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models.
Proceedings of the 2004 Design, 2004
2003
Proceedings of the Forum on specification and Design Languages, 2003