Nathalie Julien

According to our database1, Nathalie Julien authored at least 38 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Digital Twin Architecture for Ambient Assisted Living.
Proceedings of the Service Oriented, Holonic and Multi-Agent Manufacturing Systems for Industry of the Future, 2023

Modular and Distributed Architecture Using an Embedded Digital Twin for Adaptation of Assistive Technologies.
Proceedings of the Service Oriented, Holonic and Multi-Agent Manufacturing Systems for Industry of the Future, 2023

CODIT 2023 Modeling of Smart Batteries for the Realization of a Digital Twin Prototype.
Proceedings of the 9th International Conference on Control, 2023

2022
Integrating Lean Data and Digital Sobriety in Digital Twins Through Dynamic Accuracy Management.
Proceedings of the Service Oriented, Holonic and Multi-Agent Manufacturing Systems for Industry of the Future, 2022

2021
Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology.
Proceedings of the Service Oriented, Holonic and Multi-agent Manufacturing Systems for Industry of the Future, 2021

2012
Design under constraints of availability and energy for sensor node in wireless sensor network.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Power/Energy Estimator for Designing WSN Nodes with Ambient Energy Harvesting Feature.
EURASIP J. Embed. Syst., 2011

Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

2010
Virtual SoPC rad-hardening for satellite applications.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

2009
Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Estimation et optimisation de la consommation des mémoires.
Tech. Sci. Informatiques, 2008

High-Level Interconnect Delay and Power Estimation.
J. Low Power Electron., 2008

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Méthodes et outils d'estimation de la consommation de code embarqué sur processeur.
Tech. Sci. Informatiques, 2007

2006
Memory Aware High-Level Synthesis for Embedded Systems
CoRR, 2006

A Memory Aware High Level Synthesis Too
CoRR, 2006

Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power
CoRR, 2006

Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

An FPGA Power Aware Design Flow.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A high level SoC power estimation based on IP modeling.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications.
EURASIP J. Adv. Signal Process., 2005

Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

2004
Panorama des outils d'analyse et d'optimisation de la consommation dans les systèmes sur puce (SoC).
Ann. des Télécommunications, 2004

SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.
Proceedings of the Integrated Circuit and System Design, 2004

A Memory Aware High Level Synthesis Tool .
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A memory aware behavioral synthesis tool for real-time VLSI circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A Complete Methodology for Memory Optimization in DSP Applications.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Memory Aware HLS and the Implementation of Ageing Vectors.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors.
Proceedings of the 2004 Design, 2004

Memory accesses management during high level synthesis.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT.
J. VLSI Signal Process., 2003

Power Consumption Modeling and Characterization of the TI C6201.
IEEE Micro, 2003

2002
Power Consumption Estimation of a C Program for Data-Intensive Applications.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

1999
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Adaptive filters implementation performances under power dissipation constraint.
Proceedings of the 9th European Signal Processing Conference, 1998


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