Gwenolé Corre

Orcid: 0000-0001-6085-6239

According to our database1, Gwenolé Corre authored at least 18 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic Scintillator.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

2022
A Comprehensive Survey of Visual SLAM Algorithms.
Robotics, 2022

2018
High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017
Model-driven reliability evaluation for MPSoC design.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
A Scalable Design Approach to Efficiently Map Applications on CGRAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2014
An automated design approach to map applications on CGRAs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2008
Estimation et optimisation de la consommation des mémoires.
Tech. Sci. Informatiques, 2008

2006
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI
CoRR, 2006

Memory Aware High-Level Synthesis for Embedded Systems
CoRR, 2006

A Memory Aware High Level Synthesis Too
CoRR, 2006

Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power
CoRR, 2006

2005
High-level synthesis under I/O timing and memory constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
A Memory Aware High Level Synthesis Tool .
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A memory aware behavioral synthesis tool for real-time VLSI circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Memory Aware HLS and the Implementation of Ageing Vectors.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Memory accesses management during high level synthesis.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004


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