Loïc Lagadec

According to our database1, Loïc Lagadec authored at least 60 papers between 1998 and 2021.

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Bibliography

2021
Benchmarking Quantized Neural Networks on FPGAs with FINN.
CoRR, 2021

2020
Advances in Smalltalk technologies.
Sci. Comput. Program., 2020

Automated exploration of homomorphic encryption scheme input parameters.
J. Inf. Secur. Appl., 2020

Menhir: Generic High-Speed FPGA Model-Checker.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
A New Leader Election Algorithm based on the WBS Algorithm Dedicated to Smart-cities.
Proceedings of the 3rd International Conference on Future Networks and Distributed Systems, 2019

Temperature-based models of batteries for the simulation of Wireless Sensor Networks.
Proceedings of the 3rd International Conference on Future Networks and Distributed Systems, 2019

Designing a combined personal communicator and data entry terminal for disaster relief & remote operations.
Proceedings of the IEEE Global Humanitarian Technology Conference, 2019

2018
An Integrated Toolchain for Overlay-centric System-on-chip.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Fast Evaluation of Homomorphic Encryption Schemes Based on Ring-LWE.
Proceedings of the 9th IFIP International Conference on New Technologies, 2018

DoTRo: A New Dominating Tree Routing Algorithm for Efficient and Fault-Tolerant Leader Election in WSNs and IoT Networks.
Proceedings of the Mobile, Secure, and Programmable Networking, 2018

Detecting gaps and voids in WSNs and IoT networks: the minimum x-coordinate based method.
Proceedings of the 2nd International Conference on Future Networks and Distributed Systems, 2018

Detecting gaps and voids in WSNs and IoT networks: the angle-based method.
Proceedings of the 2nd International Conference on Future Networks and Distributed Systems, 2018

CupCarbon-Lab: An IoT emulator.
Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018

2017
A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Extended overlay architectures for heterogeneous FPGA cluster management.
J. Syst. Archit., 2017

PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption Schemes.
Proceedings of the 14th International Joint Conference on e-Business and Telecommunications (ICETE 2017), 2017

Asserting causal properties in High Level Synthesis.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA.
ACM Trans. Embed. Comput. Syst., 2016

Demo: Overlay architectures for heterogeneous FPGA cluster management.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Role Framework to Support Collaborative Virtual Prototyping of System of Systems.
Proceedings of the 24th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2015

A role language to interpret multi-formalism System of systems models.
Proceedings of the Annual IEEE Systems Conference, 2015

A Meta Model Supporting Both Hardware and Smalltalk-Based Execution of Fpga Circuits.
Proceedings of the International Workshop on Smalltalk Technologies, 2015

2014
Model-driven physical-design automation for FPGAs: fast prototyping and legacy reuse.
Softw. Pract. Exp., 2014

International workshop on smalltalk technologies 2011 special issue.
Softw. Pract. Exp., 2014

Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging.
Sci. Comput. Program., 2014

Preface to the special issue on advances in Smalltalk based systems.
Sci. Comput. Program., 2014

A prototyping platform for virtual reconfigurable units.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Virtual prototyping of R2D NASIC based FPGA.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Flexible Model-Based Simulation as a System's Design Driver.
Proceedings of the Poster Workshop at the 2014 Complex Systems Design & Management International Conference co-located with 5th International Conference on Complex System Design & Management (CSD&M 2014), 2014

2013
Introduction.
Tech. Sci. Informatiques, 2013

A Model-Driven Approach to Enhance Tool Interoperability Using the Theory of Models of Computation.
Proceedings of the Software Language Engineering - 6th International Conference, 2013

Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Behavioral Systel Level Power Consumption Modeling of Mobile Video Streaming applications
CoRR, 2012

A framework for high-level synthesis of heterogeneous MP-SoC.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Experiment Centric Teaching for Reconfigurable Processors.
Int. J. Reconfigurable Comput., 2011

Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010).
Int. J. Reconfigurable Comput., 2011

FPGA physical-design automation using Model-Driven Engineering.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

FPGA SDK for nanoscale architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Fast prototyping environment for embedded reconfigurable units.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Regular 2D NASIC-based architecture and design space exploration.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

MDE-based FPGA physical design: fast model-driven prototyping with Smalltalk.
Proceedings of the International Workshop on Smalltalk Technologies, 2011

2010
Session Teaching Reconfigurable Processor: the Biniou Approach.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Virtual SoPC rad-hardening for satellite applications.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Smalltalk debug lives in the matrix.
Proceedings of the International Workshop on Smalltalk Technologies, 2010

2009
Toolset for nano-reconfigurable computing.
Microelectron. J., 2009

Towards a framework for designing applications onto hybrid nano/CMOS fabrics.
Microelectron. J., 2009

Multilevel Simulation of Heterogeneous Reconfigurable Platforms.
Int. J. Reconfigurable Comput., 2009

Software-like debugging methodology for reconfigurable platforms.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2006
Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques.
Tech. Sci. Informatiques, 2006

The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA.
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006

2005
Compiler level integration of a portable CAD framework for reconfigurable circuits.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators.
Proceedings of the Computer Systems: Architectures, 2004

2002
A LUT based Approach for High Level Synthesis on FPGAs.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001
Placing, Routing, and Editing Virtual FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

1999
Object Oriented Approach for Modeling Digital Circuits.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

1998
A 6200 Model and Editor Based on Object Technology.
Proceedings of the Field-Programmable Logic and Applications, 1998


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