Nikhil Puri

According to our database, Nikhil Puri authored at least 2 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 38.1Mb/mm² SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute.

Tsung-Yung Jonathan Chang, Yen-Huei Chen, K. Venkateswara Reddy, Nikhil Puri, Teja Masina, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Ku-Feng Lin, Ming-Hung Chang, Ching-Wei Wu, Robin Lee, Yih Wang, Hung-Jen Liao, Quincy Li, Ping-Wei Wang, Geoffrey Yeap

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2017

A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET.

Vinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017