Ching-Wei Wu

According to our database1, Ching-Wei Wu authored at least 5 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
Study of Scraping guide Ways Inspection.
J. Comput., 2014

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2004
Failure Factor Based Yield Enhancement for SRAM Designs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004


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