Geoffrey Yeap

Orcid: 0000-0002-7767-7656

According to our database1, Geoffrey Yeap authored at least 14 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V<sub>MIN</sub> Applications.
IEEE J. Solid State Circuits, 2021

2020
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Holistic technology optimization and key enablers for 7nm mobile SoC.
Proceedings of the Symposium on VLSI Circuits, 2015

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Improved device variability in scaled MOSFETs with deeply retrograde channel profile.
Microelectron. Reliab., 2014

Technology-design-manufacturing co-optimization for advanced mobile SoCs.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011
FinFET based SRAM bitcell design for 32 nm node and below.
Microelectron. J., 2011

2010
BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010


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