Ulrich Kühne
Orcid: 0000-0002-0855-8223Affiliations:
- Telecom Paris, Department of Communication and Electronics (COMELEC), France
- University of Bremen, Institute of Computer Architecture, Germany (PhD 2009)
According to our database1,
Ulrich Kühne
authored at least 47 papers
between 2005 and 2022.
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Bibliography
2022
Finding Optimal Moving Target Defense Strategies: A Resilience Booster for Connected Cars.
Inf., 2022
2021
IACR Cryptol. ePrint Arch., 2021
CAAI Trans. Intell. Technol., 2021
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021
Moving Target Defense Strategy in Critical Embedded Systems: A Game-theoretic Approach.
Proceedings of the 26th IEEE Pacific Rim International Symposium on Dependable Computing, 2021
Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural Networks.
Proceedings of the Applied Cryptography and Network Security, 2021
2020
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
2019
LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Run or Hide? Both! A Method Based on IPv6 Address Switching to Escape While Being Hidden.
Proceedings of the 6th ACM Workshop on Moving Target Defense, 2019
2018
IPSJ Trans. Syst. LSI Des. Methodol., 2018
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2016
Formal verification of integer multipliers by combining Gröbner basis with logic reduction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the 2nd International Workshop on Synthesis of Complex Parameters, 2015
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Formal Methods Syst. Des., 2014
Proceedings of the Tests and Proofs - 8th International Conference, 2014
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Proceedings of the 2014 Forum on Specification and Design Languages, 2014
Verifying consistency between activity diagrams and their corresponding OCL contracts.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
Parametric Verification and Test Coverage for Hybrid Automata using the inverse Method.
Int. J. Found. Comput. Sci., 2013
Proceedings of the 1st French Singaporean Workshop on Formal Methods and Applications, 2013
2012
Proceedings of the Graph Transformations - 6th International Conference, 2012
Proceedings of the FM 2012: Formal Methods, 2012
2011
Towards Automatic Property Generation for the Formal Verification of Bus Bridges.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
IEEE Embed. Syst. Lett., 2010
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010
2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the Applications of Evolutionary Computing, 2006
2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005