Ning-Chi Huang

Orcid: 0000-0003-4663-9099

According to our database¹, Ning-Chi Huang authored at least 17 papers between 2017 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2025

Speculate Deep and Accurate: Lossless and Training-Free Acceleration for Offloaded LLMs via Substitute Speculative Decoding.

[BibT_eX]

[DOI]

Mohamed S. Abdelfattah

Kai-Chiang Wu

CoRR, September, 2025

Palu: KV-Cache Compression with Low-Rank Projection.

[BibT_eX]

[DOI]

Mohamed S. Abdelfattah

Kai-Chiang Wu

Proceedings of the Thirteenth International Conference on Learning Representations, 2025

Integrating Neural Architecture Search and Rematerialization for Efficient On-Device Learning.

[BibT_eX]

[DOI]

Chih-Ling Chen

Kai-Chiang Wu

Ning-Chi Huang

Proceedings of the Genetic and Evolutionary Computation Conference, 2025

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2025

2024

V"Mean"ba: Visual State Space Models only need 1 hidden dimension.

[BibT_eX]

[DOI]

CoRR, 2024

ELSA: Exploiting Layer-wise N:M Sparsity for Vision Transformer Acceleration.

[BibT_eX]

[DOI]

CoRR, 2024

Palu: Compressing KV-Cache with Low-Rank Projection.

[BibT_eX]

[DOI]

CoRR, 2024

FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

ELSA: Exploiting Layer-wise N: M Sparsity for Vision Transformer Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023

Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs.

[BibT_eX]

[DOI]

Ning-Chi Huang

Chao-Wei Cheng

Kai-Chiang Wu

IEEE Trans. Very Large Scale Integr. Syst., 2022

2021

An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

2020

Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

2019

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs.

[BibT_eX]

[DOI]

Ning-Chi Huang

Yu-Guang Chen

Kai-Chiang Wu

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications.

[BibT_eX]

[DOI]

Ning-Chi Huang

Szu-Ying Chen

Kai-Chiang Wu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017

Analysis and optimization of variable-latency designs in the presence of timing variability.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Ning-Chi Huang

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...