Mohamed S. Abdelfattah

Orcid: 0000-0002-4568-8932

According to our database1, Mohamed S. Abdelfattah authored at least 41 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision.
CoRR, 2024

Encodings for Prediction-based Neural Architecture Search.
CoRR, 2024

On Latency Predictors for Neural Architecture Search.
CoRR, 2024

Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel.
CoRR, 2024

Fast Inference Through The Reuse Of Attention Maps In Diffusion Models.
CoRR, 2024

2023
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search.
CoRR, 2023

Are We There Yet? Product Quantization and its Hardware Acceleration.
CoRR, 2023

DiviML: A Module-based Heuristic for Mapping Neural Networks onto Heterogeneous Platforms.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs.
Proceedings of the International Conference on Field Programmable Technology, 2023

BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Multi-Predict: Few Shot Predictors For Efficient Neural Architecture Search.
Proceedings of the International Conference on Automated Machine Learning, 2023

Zero-Cost Operation Scoring in Differentiable Architecture Search.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
BLOX: Macro Neural Architecture Search Benchmark and Algorithms.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2021
Zero-Cost Proxies Meet Differentiable Architecture Search.
CoRR, 2021

Are Mobile DNN Accelerators Accelerating DNNs?
Proceedings of the EMDL@MobiSys 2021: Proceedings of the 5th International Workshop on Embedded and Mobile Deep Learning, 2021

NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition.
Proceedings of the 9th International Conference on Learning Representations, 2021

Zero-Cost Proxies for Lightweight NAS.
Proceedings of the 9th International Conference on Learning Representations, 2021

Temporal Kernel Consistency for Blind Video Super-Resolution.
Proceedings of the IEEE/CVF International Conference on Computer Vision Workshops, 2021

2020
BRP-NAS: Prediction-based NAS using GCNs.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020


Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Journey Towards Tiny Perceptual Super-Resolution.
Proceedings of the Computer Vision - ECCV 2020, 2020

Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
ShrinkML: End-to-End ASR Model Compression Using Reinforcement Learning.
Proceedings of the Interspeech 2019, 2019

2018
Flexibility: FPGAs and CAD in Deep Learning Acceleration.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Harnessing Numerical Flexibility for Deep Learning on FPGAs.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Design and Applications for Embedded Networks-on-Chip on FPGAs.
IEEE Trans. Computers, 2017

2016
Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses.
IEEE Trans. Very Large Scale Integr. Syst., 2016

LYNX: CAD for FPGA-based networks-on-chip.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Design and simulation tools for Embedded NOCs on FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Take the Highway: Design for Embedded NoCs on FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
Networks-on-Chip for FPGAs: Hard, Soft or Mixed?
ACM Trans. Reconfigurable Technol. Syst., 2014

The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays.
IEEE Micro, 2014

Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL.
Proceedings of the International Workshop on OpenCL, 2014

2013
The power of communication: Energy-efficient NOCS for FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Design tradeoffs for hard and soft FPGA-based Networks-on-Chip.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012


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